forked from M-Labs/artiq
conda: bump migen, misoc
* xilinx ODDR2 SRTYPE * flterm leak * I/ODELAY VTC/reset sequencing * sayma SDRAM clock buffer LOC
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@ -14,8 +14,8 @@ requirements:
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run:
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- python >=3.5.3,<3.6
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- setuptools 33.1.1
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- migen 0.7 py35_20+git1f82faa
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- misoc 0.10 py35_0+gitd167deff
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- migen 0.7 py35_21+git881741b
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- misoc 0.10 py35_9+git103bb3a8
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- jesd204b 0.5
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- microscope
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- binutils-or1k-linux >=2.27
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