forked from M-Labs/artiq
kusddrphy: use first and last tap that yield many valid reads
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@ -1,7 +1,6 @@
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#[cfg(has_ddrphy)]
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mod ddr {
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use core::{ptr, fmt};
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use core::cell::Cell;
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use csr::{dfii, ddrphy};
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use sdram_phy::{self, spin_cycles};
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use sdram_phy::{DFII_COMMAND_CS, DFII_COMMAND_WE, DFII_COMMAND_CAS, DFII_COMMAND_RAS,
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@ -317,13 +316,14 @@ mod ddr {
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for n in 0..DQS_SIGNAL_COUNT {
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ddrphy::dly_sel_write(1 << (DQS_SIGNAL_COUNT - n - 1));
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ddrphy::rdly_dq_rst_write(1);
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let delay = Cell::new(0);
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let incr_delay_until = |expected| {
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while delay.get() < DDRPHY_MAX_DELAY {
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let mut working = true;
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for _ in 0..1024 {
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let find_edge = |which| {
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// Find the first (which=true) or last (which=false) tap that leads to a
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// sufficiently high number of correct reads.
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let mut last_valid = 0;
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ddrphy::rdly_dq_rst_write(1);
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for delay in 0..DDRPHY_MAX_DELAY {
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let mut valid = true;
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for _ in 0..256 {
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sdram_phy::command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|
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DFII_COMMAND_RDDATA);
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spin_cycles(15);
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@ -333,40 +333,26 @@ mod ddr {
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let addr = DFII_PIX_RDDATA_ADDR[p].offset(offset as isize);
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let data = prs[DFII_PIX_DATA_SIZE * p + offset];
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if ptr::read_volatile(addr) as u8 != data {
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working = false;
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valid = false;
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}
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}
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}
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}
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if working == expected {
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break
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if valid {
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last_valid = delay;
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if which {
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break;
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}
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}
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delay.set(delay.get() + 1);
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ddrphy::rdly_dq_inc_write(1);
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}
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last_valid
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};
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// Find smallest working delay
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incr_delay_until(true);
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let min_delay = delay.get();
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// Get a bit further into the working zone
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#[cfg(kusddrphy)]
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for _ in 0..32 {
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delay.set(delay.get() + 1);
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ddrphy::rdly_dq_inc_write(1);
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}
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#[cfg(not(kusddrphy))]
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{
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delay.set(delay.get() + 1);
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ddrphy::rdly_dq_inc_write(1);
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}
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// Find largest working delay
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incr_delay_until(false);
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let max_delay = delay.get();
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let min_delay = find_edge(true);
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let max_delay = find_edge(false);
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log!(logger, "{}:{:02}-{:02} ", DQS_SIGNAL_COUNT - n - 1,
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min_delay, max_delay);
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