forked from M-Labs/artiq
sdram: reject read delay wrap arounds
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parent
65379b1f7a
commit
276b0c7f06
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@ -321,6 +321,8 @@ mod ddr {
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let mut min_delay = 0;
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let mut have_min_delay = false;
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let mut max_delay = 0;
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let mut have_max_delay = false;
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let mut have_invalid = 0;
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ddrphy::rdly_dq_rst_write(1);
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@ -328,7 +330,7 @@ mod ddr {
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let mut valid = true;
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for _ in 0..256 {
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sdram_phy::command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|
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DFII_COMMAND_RDDATA);
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DFII_COMMAND_RDDATA);
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spin_cycles(15);
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for p in 0..DFII_NPHASES {
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@ -347,7 +349,14 @@ mod ddr {
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min_delay = delay;
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have_min_delay = true;
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}
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max_delay = delay;
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if !have_max_delay {
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max_delay = delay;
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}
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} else if have_min_delay {
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have_invalid += 1;
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if have_invalid >= 10 {
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have_max_delay = true;
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}
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}
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ddrphy::rdly_dq_inc_write(1);
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}
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