forked from M-Labs/artiq
ad53xx: port monitor, moninj dashboard, kc705 target
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@ -224,8 +224,8 @@ def setup_from_ddb(ddb):
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channel = v["arguments"]["channel"]
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widget = _WidgetDesc(k, comment, _DDSWidget, (bus_channel, channel, k))
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description.add(widget)
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elif (v["module"] == "artiq.coredevice.ad5360"
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and v["class"] == "AD5360"):
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elif (v["module"] == "artiq.coredevice.ad53xx"
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and v["class"] == "AD53XX"):
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spi_device = v["arguments"]["spi_device"]
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spi_device = ddb[spi_device]
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while isinstance(spi_device, str):
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@ -1,10 +1,10 @@
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from migen import *
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from artiq.coredevice.spi2 import SPI_CONFIG_ADDR, SPI_DATA_ADDR
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from artiq.coredevice.ad5360 import _AD5360_CMD_DATA, _AD5360_WRITE_CHANNEL
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from artiq.coredevice.ad53xx import AD53XX_CMD_DATA, ad53xx_cmd_write_ch
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class AD5360Monitor(Module):
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class AD53XXMonitor(Module):
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def __init__(self, spi_rtlink, ldac_rtlink=None, cs_no=0, cs_onehot=False, nchannels=32):
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self.probes = [Signal(16) for i in range(nchannels)]
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@ -39,8 +39,10 @@ class AD5360Monitor(Module):
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)
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]
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writes = {(_AD5360_CMD_DATA | _AD5360_WRITE_CHANNEL(i)) >> 16: t.eq(spi_oif.data[8:24])
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for i, t in enumerate(write_targets)}
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writes = {
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ad53xx_cmd_write_ch(channel=i, value=0, op=AD53XX_CMD_DATA) >> 16:
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t.eq(spi_oif.data[8:24])
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for i, t in enumerate(write_targets)}
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self.sync.rio_phy += [
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If(spi_oif.stb & (spi_oif.address == SPI_DATA_ADDR),
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Case(spi_oif.data[24:], writes)
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@ -17,7 +17,7 @@ from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
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dds, spi2, ad5360_monitor)
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dds, spi2, ad53xx_monitor)
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from artiq.build_soc import build_artiq_soc
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from artiq import __version__ as artiq_version
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@ -351,7 +351,7 @@ class NIST_CLOCK(_StandaloneBase):
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self.submodules += ldac_phy
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rtio_channels.append(rtio.Channel.from_phy(ldac_phy))
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dac_monitor = ad5360_monitor.AD5360Monitor(sdac_phy.rtlink, ldac_phy.rtlink)
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dac_monitor = ad53xx_monitor.AD53XXMonitor(sdac_phy.rtlink, ldac_phy.rtlink)
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self.submodules += dac_monitor
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sdac_phy.probes.extend(dac_monitor.probes)
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