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6,163 Commits 63 Branches 34 Tags 19 MiB
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6163 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 4b4374f76a sayma: register_jref for JESD204. Closes #904 2018-01-23 12:19:15 +08:00
Sebastien Bourdeauducq 763aefacff kasli: fix typo 2018-01-23 12:10:54 +08:00
Sebastien Bourdeauducq c7b148a704 kasli: when using both GTP clocks, send REFCLK0 to PLL0 and REFCLK1 to PLL1 2018-01-23 12:08:10 +08:00
Sebastien Bourdeauducq d6157514c7 gtp_7series: flexible QPLL channel selection 2018-01-23 12:03:09 +08:00
Sebastien Bourdeauducq 9f87c34a94 kasli: fix QPLL instantiation 2018-01-23 10:39:31 +08:00
Sebastien Bourdeauducq 98a5607634 gtp_7series: set clock muxes correctly for second QPLL channel 2018-01-23 10:39:20 +08:00
Sebastien Bourdeauducq 25fee1a0bb gtp_7series: use QPLL second channel 2018-01-23 10:15:49 +08:00
Sebastien Bourdeauducq 031d7ff020 kasli: keep using second QPLL channel for DRTIO satellite 2018-01-23 10:13:10 +08:00
Sebastien Bourdeauducq 626075cbc1 gtp_7series: simplify TX clocking 2018-01-23 09:49:23 +08:00
Robert Jördens 472840f16b conda: bump migen/misoc 
* kasli clock constraint
* vivado false paths
 2018-01-22 20:32:18 +01:00
Robert Jördens 74b7baa8c5 urukul example: mmcx clock input 2018-01-22 20:30:08 +01:00
Robert Jördens a86b28def2 urukul: example additions 
* relax timings for faster spi xfers
* continuous readback test to explore spi speed limit
 2018-01-22 20:29:30 +01:00
Robert Jördens 5a9035b122 urukul: faster spi clock 2018-01-22 18:27:40 +00:00
Robert Jördens ca1fdaa190 ad9910: relax timing for faster spi clock 2018-01-22 18:27:40 +00:00
Sebastien Bourdeauducq 0d73401365 conda: bump migen+misoc 2018-01-23 01:28:10 +08:00
Sebastien Bourdeauducq 401e57d41c gtp_7series: fix nchannels assert 2018-01-23 01:28:01 +08:00
Sebastien Bourdeauducq aa62e91487 kasli: add DRTIO targets (no firmware) 2018-01-23 01:27:40 +08:00
Sebastien Bourdeauducq 296ac35f5d sayma_amc: SFP TX disable is active-high 2018-01-23 00:32:09 +08:00
Sebastien Bourdeauducq 77192256ea kc705: style 2018-01-23 00:02:35 +08:00
Sebastien Bourdeauducq ab7c49d6d0 sayma_amc: raise error on invalid variant 2018-01-23 00:02:16 +08:00
Sebastien Bourdeauducq c1ac3b66b1 sayma_rtm: fix 8fe463d4a 2018-01-23 00:01:45 +08:00
Sebastien Bourdeauducq 53facfef13 sayma: build fixes 2018-01-22 18:33:22 +08:00
Sebastien Bourdeauducq 25f3feeda8 refactor targets 2018-01-22 18:25:10 +08:00
Sebastien Bourdeauducq 5198c224a2 sayma,kasli: use new pin names 2018-01-22 11:51:07 +08:00
whitequark 8598e475e9 artiq_flash: fix a refactoring mistake. 2018-01-20 08:30:42 +00:00
Sebastien Bourdeauducq c3323f0d57 hmc830: improve lock failure error report 2018-01-20 15:42:53 +08:00
whitequark 115aa0d0d6 artiq_flash: support load action for Sayma RTM FPGA. 2018-01-20 07:23:50 +00:00
whitequark 94592c7a4c artiq_flash: unify flash handling in XC7 and Sayma programmers. 2018-01-20 07:23:50 +00:00
whitequark 1ffabac06f artiq_flash: use atexit for tempfile cleanup. 2018-01-20 07:23:50 +00:00
whitequark ab9eb56ceb setup.py: migen now works on Python 3.6, relax version check. 2018-01-20 07:23:50 +00:00
Florent Kermarrec 8fe463d4a0 sayma_rtm: add UART loopback to easily know if rtm fpga is alive 2018-01-20 06:04:34 +01:00
Florent Kermarrec 74ce7319d3 sayma: reduce serwb linerate to 625Mbps (make it work on saymas with 1.8v issue, related?) 2018-01-20 06:04:18 +01:00
whitequark f4022ba872 remoting: avoid a race condition. 2018-01-20 01:30:44 +00:00
whitequark 83278a6edb artiq_flash: fix a refactoring bug. 2018-01-20 01:30:44 +00:00
hartytp 37fa3b29da firmware: add register dump on HMC830 lock timeout. 2018-01-20 00:19:31 +00:00
whitequark 934bc53cb5 artiq_devtool: refactor. 2018-01-19 20:35:35 +00:00
whitequark ebd02c4f43 artiq_flash: fix typo. 2018-01-19 18:53:49 +00:00
whitequark 1c7cb737ca artiq_flash: refactor. 2018-01-19 17:45:49 +00:00
whitequark bcc39a8c9d artiq_flash: add --dry-run option. 2018-01-19 17:45:49 +00:00
whitequark 323c7e66cf artiq_devtool: fix help message. 2018-01-19 17:45:49 +00:00
Florent Kermarrec 9eb13aba3c liboard_artiq/hmc830_7043: allow sysref digital/analog delay configuration (will need to be adjusted for jesd subclass1) 2018-01-19 17:19:02 +01:00
Florent Kermarrec d27727968c add artix7 gtp (3gbps), share clock aligner with gth_ultrascale 2018-01-19 12:17:54 +01:00
Sebastien Bourdeauducq cdbf95d46a kasli: fix permissions 2018-01-19 18:31:20 +08:00
whitequark 3c0b164e4d artiq_devtool: update for new board file convention. 
Also fix a typo in documentation.
 2018-01-19 09:43:03 +00:00
whitequark 0cdbc5544a doc: update DEVELOPER_NOTES. 2018-01-19 09:38:06 +00:00
whitequark b1453eb856 Revert "conda: remove openocd version constraint." 
This reverts commit 3eb882b6b7.

Fixes #892.
 2018-01-19 08:28:36 +00:00
whitequark 4fd236d234 artiq_flash: cache transferred artifacts. 2018-01-19 08:28:04 +00:00
whitequark 06388e21b7 doc: update DEVELOPER_NOTES. 2018-01-19 07:59:23 +00:00
whitequark 3922a7c64b artiq_devtool: make locking reentrant. 2018-01-19 07:58:58 +00:00
whitequark b553804e5a artiq_flash: implement network transparency. 2018-01-19 07:39:55 +00:00