forked from M-Labs/artiq
urukul: faster spi clock
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@ -15,7 +15,7 @@ _SPIT_CFG_WR = 2
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_SPIT_CFG_RD = 16
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_SPIT_ATT_WR = 2
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_SPIT_ATT_RD = 16
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_SPIT_DDS_WR = 16
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_SPIT_DDS_WR = 3
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_SPIT_DDS_RD = 16
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# CFG configuration register bit offsets
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