sjm
/
zc706
forked from M-Labs/zynq-rs
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
199 Commits 3 Branches 0 Tags 780 KiB
Commit Graph

172 Commits

Author SHA1 Message Date
Astro ff96bf903b zynq::ddr: only enable_ddr if no clock yet 
that's only an issue for the cora z7
 2019-11-07 00:13:50 +01:00
Astro d2df5652d0 Revert "zynq: replace unnecessary slcr::unlocked with new" 
This reverts commit 6bee1f44f4.
 2019-11-07 00:13:50 +01:00
Astro eb56dda44f zynq::slcr::unlocked: fix comment 2019-11-07 00:13:50 +01:00
Astro 74c43b3477 zynq::eth::tx: clear entry.word1 for each packet 2019-11-04 02:31:40 +01:00
Astro 99a00e019b zynq::eth: implement phy::extended_status, set clock for link speed 2019-11-04 02:30:00 +01:00
Astro 961e2e1dd0 zynq::{ddr, eth}: fix clock divisor calculation 
off-by-one, didn't change behavior.
 2019-11-03 02:23:16 +01:00
Astro 04e816d99e zynq::slcr: fix a bitfield index 
that didn't solve our problems.
 2019-11-03 02:01:42 +01:00
Astro 6bee1f44f4 zynq: replace unnecessary slcr::unlocked with new 2019-10-31 20:48:07 +01:00
Astro 54e4b9281f main: rewrap linked_list_allocator 2019-10-31 19:21:02 +01:00
Astro 5c62716a99 zynq::eth: switch rx and tx descriptor words to vcell 
vcell can be initialized cleanly.
 2019-10-31 03:15:13 +01:00
Astro 1f728686ff rm ram, add linked_list_allocator on ddr 2019-10-31 01:41:10 +01:00
Astro e248d3d3b1 zynq::ddr: optimize memtest 2019-10-31 01:32:45 +01:00
Astro 91bab76ab6 zynq::ddr: fix usable ram size 2019-10-31 01:27:49 +01:00
Astro ceeaa6427e zynq::ddr: fix typo 2019-10-28 23:58:25 +01:00
Astro 7cdf6c0918 start implementation of a StaticAllocator 2019-10-28 00:43:57 +01:00
Astro fc39885d3b zynq::ddr: fix clock setup 2019-10-28 00:43:09 +01:00
Astro f199ac68b4 zynq::ddr: don't overwrite slcr.ddr_pll_ctrl 2019-10-27 22:54:34 +01:00
Astro 637bb35f43 zynq::ddr: fix memtest progress calculation 2019-10-27 20:38:35 +01:00
Astro 85bd506132 zynq::ddr: parameters 2019-10-27 20:38:06 +01:00
Astro 27114aec62 zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage 
this seems to make DDR RAM work.
 2019-10-27 20:30:56 +01:00
Astro 9b4f07f37c zynq::ddr, main: parameters, memtest 2019-10-25 23:19:34 +02:00
Astro e61d1268ac zynq::slcr: doc, fix 2019-10-25 23:18:18 +02:00
Astro a4d3360a70 zynq::slcr: implement Display for PllStatus 2019-10-25 20:38:10 +02:00
Astro 838434cdec zynq::ddr: wait for init 2019-10-25 19:15:22 +02:00
Astro 4cf5283ba8 zynq::ddr: implement reset_ddrc(), add to main 2019-10-24 01:39:14 +02:00
Astro a8886de067 zynq::ddr: implement configure_iob() 2019-10-24 01:24:12 +02:00
Astro afda48e3fe zynq::ddr: add clock_setup(), calibrate_iob_impedance() 2019-10-22 01:25:35 +02:00
Astro c046bbf8a2 move slcr, clocks, uart, eth into src/zynq/ 2019-10-21 22:19:03 +02:00
Astro 9d725bcf0f zynq::ddr: init with clock setup 2019-10-21 22:12:10 +02:00
Astro 58cf9833cc slcr: implement PllCfg and DdrClkCtrl 2019-10-21 22:10:51 +02:00
Astro 83b8bb096a add zynq::axi_gp 2019-10-19 01:46:43 +02:00
Astro b541160f38 add zynq::axi_hp 2019-10-18 23:46:00 +02:00
Björn Stein 1804c4c6e8 cortex_a9: add proper L1 cache invalidation 2019-10-18 00:11:51 +02:00
Björn Stein d87b874b21 eth: add memory barriers, reorder access 2019-10-18 00:04:22 +02:00
Björn Stein 9053166acc eth: increase desc list safety 2019-10-18 00:03:17 +02:00
Astro 4e9c38527e rm debug, delint 2019-09-29 03:01:24 +02:00
Astro a76214cb9d eth: split into Eth and EthInner 2019-09-29 02:58:17 +02:00
Astro 0f6bc68d1f eth: prepare link change detection 2019-09-29 02:30:03 +02:00
Astro 378755a0ce main: bump RX_LEN/TX_LEN to 2 2019-09-29 01:40:38 +02:00
Astro 644cc64524 eth: align DescEntries 2019-09-29 01:39:12 +02:00
Astro 4c62ce0dad main: restrict eth buffers to 1 each 2019-08-19 02:21:36 +02:00
Astro 9c73cf130d eth: wait for link 2019-08-19 02:21:02 +02:00
Astro 45ed5f6c5b abort handlers: replace panic with infinite loop 2019-08-19 01:18:12 +02:00
Astro d11e581862 main: setup smoltcp 
still panics, leading to a DataAbort
 2019-08-19 01:18:12 +02:00
Astro 3a5ed0aac6 eth: add smoltcp support 2019-08-19 01:18:12 +02:00
Astro 5603766c5d eth: enable csum offloading 
should prevent FCS errors
 2019-08-19 01:12:52 +02:00
Astro 43c3f3e4a6 eth: fix tx_clock magnitude bug 
Ethernet TX now works!
 2019-08-18 22:52:05 +02:00
Astro 4bc1d21ae9 eth: rm obsolete TODO 2019-08-18 22:44:33 +02:00
Astro bfb3a00a4e eth: derive proper mdc_clk_div from clocks 2019-08-18 22:43:56 +02:00
Astro b8818863c4 read clocks 2019-08-17 03:20:04 +02:00
Astro 1f9ad5ff62 delint 2019-08-11 00:56:54 +02:00
Astro b7690c9702 fix UART_REF_CLK 
started to become garbled.
 2019-08-07 00:27:01 +02:00
Astro d001593a36 rm bcmp 2019-08-06 22:03:23 +02:00
Astro 2db35d063f define bcmp 
other solution might be defining a non-linux target
 2019-08-06 14:15:44 +02:00
Astro b9c233b05b compile fixes 2019-07-01 00:15:17 +02:00
Astro d6b2321fee eth: fix mio_pin setup 2019-06-29 00:00:22 +02:00
Astro 9ab40daca2 eth: setup_gem0/1_clock() 2019-06-25 21:50:38 +02:00
Astro 5823d90db1 phy: implement control, status, reset 2019-06-25 21:48:47 +02:00
Astro e6827a81f3 eth tx: set net_ctrl.start_tx on sending 2019-06-25 01:46:29 +02:00
Astro 374686fd3e eth tx: set last_buffer flag 2019-06-24 02:15:11 +02:00
Astro ce74fe7299 eth: prepare tx 2019-06-22 01:39:44 +02:00
Astro ec5dda4d0a eth: add const MTU 2019-06-22 01:34:17 +02:00
Astro 6757ceb76c eth rx: error handling 2019-06-22 01:20:18 +02:00
Astro a4be03bee9 rx: PktRef 2019-06-21 01:19:04 +02:00
Astro 80f003b2c6 stdio: add print 2019-06-21 01:18:24 +02:00
Astro e5881a14ad eth rx: descriptors/buffers as refs 
avoid moving these after their addresses have been written to the qbar
 2019-06-21 00:58:18 +02:00
Astro d65398205f add a println! for convenience 2019-06-20 00:30:18 +02:00
Astro b3b65f9b74 eth: find Phy 2019-06-19 00:21:17 +02:00
Astro 54d0f3583d eth: fix io configuration 
phy detection now works
 2019-06-18 23:10:35 +02:00
Astro 1634513bc7 mmu: align l1_table 2019-06-18 19:18:47 +02:00
Astro 9bebfb49bc begin MMU implementation 2019-06-17 03:32:10 +02:00
Astro 69b65b5f72 cortex_a9 regs: allow defining bit fields 2019-06-17 01:36:11 +02:00
Astro 1e16beb707 cortex_a9::regs: use crate::regs interface 2019-06-12 00:20:23 +02:00
Astro 81a892b618 eth: recv_next() 2019-06-10 02:44:29 +02:00
Astro f92ea3b99d eth: start_tx 2019-06-09 20:28:33 +02:00
Astro f07a541c99 eth: model rx/tx state with type parameters 2019-06-09 20:10:41 +02:00
Astro 74bd81f87f eth: add safety asserts 2019-06-09 02:23:37 +02:00
Astro 824e91e6cb eth: rx/tx desc list, start_rx 2019-06-09 01:02:10 +02:00
Astro 2d7fed6c59 link again compiler_builtins 
required for memset etc
 2019-06-09 01:00:58 +02:00
Astro d447f1cc45 main: probe for PHYs 2019-06-04 23:50:11 +02:00
Astro b9ca9324f0 eth: fix initialization 2019-06-04 23:48:33 +02:00
Astro 6d15b82a3e cortex_a9::regs: init U bit for unaligned access 2019-06-04 23:47:23 +02:00
Astro acf995d7da soft_reset: rm unreachable! 2019-05-31 00:19:20 +02:00
Astro bf4f5108f4 main: add UART_RATE 2019-05-31 00:19:01 +02:00
Astro 2df74cc055 add static exception handling 2019-05-30 20:30:19 +02:00
Astro b13bf72c17 eth: begin phy communication 2019-05-30 02:42:42 +02:00
Astro 5b15bb5c0a main: make boot_core0() naked 2019-05-30 02:41:44 +02:00
Astro c0610ad66a slcr: init gem* rclk/clk 2019-05-30 02:26:19 +02:00
Astro ee7ae7f7cc slcr: add soft_rst() 2019-05-30 00:24:51 +02:00
Astro b961526b97 uart: remove type conversion from baud_rate_gen 2019-05-30 00:22:45 +02:00
Astro a645d13f4b add uart panic handler 2019-05-28 00:28:35 +02:00
Astro 75bb755327 extend linker script 2019-05-27 22:38:10 +02:00
Astro d10ffe9eb9 eth: setup mio_pins, configure net_cfg 2019-05-25 03:06:39 +02:00
Astro 51c39f032e run with the cora z7-10 2019-05-25 02:38:48 +02:00
Astro b3da0e4c93 slcr: define all mio_pin regs, typed io_type 2019-05-25 02:34:58 +02:00
Astro 6bf210366a regs: properly emit doc_comments 2019-05-24 23:49:49 +02:00
Astro 56c2f1d833 eth: add net_status, phy_maint registers 2019-05-24 00:20:59 +02:00
Astro ad77e3dc04 eth: add net_cfg register 2019-05-24 00:06:29 +02:00
Astro 402b8c9ab1 eth: no unsafe, note, add qbar register fields 2019-05-23 23:18:36 +02:00
Astro 1033648c3e add l1_cache_init() 2019-05-23 19:05:06 +02:00