move slcr, clocks, uart, eth into src/zynq/

master
Astro 3 years ago
parent 9d725bcf0f
commit c046bbf8a2
  1. 19
      src/main.rs
  2. 2
      src/stdio.rs
  3. 2
      src/zynq/clocks.rs
  4. 4
      src/zynq/ddr/mod.rs
  5. 4
      src/zynq/eth/mod.rs
  6. 0
      src/zynq/eth/phy/control.rs
  7. 0
      src/zynq/eth/phy/id.rs
  8. 0
      src/zynq/eth/phy/mod.rs
  9. 0
      src/zynq/eth/phy/status.rs
  10. 0
      src/zynq/eth/regs.rs
  11. 0
      src/zynq/eth/rx.rs
  12. 0
      src/zynq/eth/tx.rs
  13. 4
      src/zynq/mod.rs
  14. 0
      src/zynq/slcr.rs
  15. 0
      src/zynq/uart/baud_rate_gen.rs
  16. 4
      src/zynq/uart/mod.rs
  17. 0
      src/zynq/uart/regs.rs

@ -18,11 +18,7 @@ use smoltcp::socket::SocketSet;
mod regs;
mod cortex_a9;
mod clocks;
mod slcr;
mod uart;
mod stdio;
mod eth;
mod zynq;
use crate::regs::{RegisterR, RegisterW};
@ -90,7 +86,8 @@ const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
fn main() {
println!("Main.");
let clocks = clocks::CpuClocks::get();
let clocks = zynq::clocks::CpuClocks::get();
println!("Clocks: {:?}", clocks);
println!("CPU speeds: {}/{}/{}/{} MHz",
clocks.cpu_6x4x() / 1_000_000,
@ -98,17 +95,17 @@ fn main() {
clocks.cpu_2x() / 1_000_000,
clocks.cpu_1x() / 1_000_000);
let eth = eth::Eth::default(HWADDR.clone());
let eth = zynq::eth::Eth::default(HWADDR.clone());
println!("Eth on");
const RX_LEN: usize = 2;
let mut rx_descs: [eth::rx::DescEntry; RX_LEN] = unsafe { uninitialized() };
let mut rx_buffers = [[0u8; eth::MTU]; RX_LEN];
let mut rx_descs: [zynq::eth::rx::DescEntry; RX_LEN] = unsafe { uninitialized() };
let mut rx_buffers = [[0u8; zynq::eth::MTU]; RX_LEN];
// Number of transmission buffers (minimum is two because with
// one, duplicate packet transmission occurs)
const TX_LEN: usize = 2;
let mut tx_descs: [eth::tx::DescEntry; TX_LEN] = unsafe { uninitialized() };
let mut tx_buffers = [[0u8; eth::MTU]; TX_LEN];
let mut tx_descs: [zynq::eth::tx::DescEntry; TX_LEN] = unsafe { uninitialized() };
let mut tx_buffers = [[0u8; zynq::eth::MTU]; TX_LEN];
let eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
//let mut eth = eth.start_tx(&mut tx_descs, &mut tx_buffers);
let mut eth = eth.start_tx(
@ -178,7 +175,7 @@ fn main() {
fn panic(info: &core::panic::PanicInfo) -> ! {
println!("\nPanic: {}", info);
slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
zynq::slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
loop {}
}

@ -1,4 +1,4 @@
use crate::uart::Uart;
use crate::zynq::uart::Uart;
const UART_RATE: u32 = 115_200;
static mut UART: Option<Uart> = None;

@ -1,5 +1,5 @@
use crate::slcr;
use crate::regs::RegisterR;
use super::slcr;
#[cfg(feature = "target_zc706")]
const PS_CLK: u32 = 33_333_333;

@ -1,6 +1,6 @@
use crate::regs::RegisterW;
use crate::slcr;
use crate::clocks::CpuClocks;
use super::slcr;
use super::clocks::CpuClocks;
/// Micron MT41J256M8HX-15E: 667 MHz
const DDR_FREQ: u32 = 666_666_666;

@ -1,7 +1,7 @@
use crate::regs::*;
use crate::slcr;
use crate::println;
use crate::clocks::CpuClocks;
use super::slcr;
use super::clocks::CpuClocks;
pub mod phy;
use phy::{Phy, PhyAccess};

@ -1,3 +1,7 @@
pub mod slcr;
pub mod clocks;
pub mod uart;
pub mod eth;
pub mod axi_hp;
pub mod axi_gp;
pub mod ddr;

@ -1,8 +1,8 @@
use core::fmt;
use crate::regs::*;
use crate::slcr;
use crate::clocks::CpuClocks;
use super::slcr;
use super::clocks::CpuClocks;
mod regs;
mod baud_rate_gen;
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