zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage

this seems to make DDR RAM work.
master
Astro 3 years ago
parent 9b4f07f37c
commit 27114aec62
  1. 2
      src/zynq/clocks.rs

@ -102,7 +102,7 @@ impl CpuClocks {
);
let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter()
.filter(|(fdiv_max, _)| fdiv <= *fdiv_max)
.last()
.nth(0)
.expect("PLL_FDIV_LOCK_PARAM")
.1.clone();
regs.ddr_pll_cfg.write(

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