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@ -1,5 +1,6 @@ |
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use core::ops::{Deref, DerefMut}; |
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use crate::{register, register_bit, register_bits, regs::*}; |
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use crate::cortex_a9::asm; |
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use super::{MTU, regs}; |
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/// Descriptor entry
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@ -62,6 +63,8 @@ impl<'a> DescList<'a> { |
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.last_buffer(true) |
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); |
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} |
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// Ensure the descriptor words get written before they are read.
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asm::dsb(); |
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DescList { |
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// Shorten the list of descriptors to the required number.
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@ -79,8 +82,8 @@ impl<'a> DescList<'a> { |
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let list_len = self.list.len(); |
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let entry = &mut self.list[self.next]; |
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if entry.word1.read().used() { |
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entry.word1.modify(|_, w| w.length(length as u16)); |
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let buffer = &mut self.buffers[self.next][0..length]; |
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entry.word1.modify(|_, w| w.length(length as u16)); |
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self.next += 1; |
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if self.next >= list_len { |
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@ -105,7 +108,14 @@ pub struct PktRef<'a> { |
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impl<'a> Drop for PktRef<'a> { |
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fn drop(&mut self) { |
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// Ensure that all writes to the buffer have finished before
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// they are read again.
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asm::dmb(); |
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self.entry.word1.modify(|_, w| w.used(false)); |
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// Ensure that the descriptor write has finished before it is
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// read again, and (by DSB, not just DMB) that it has been
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// written before the register access.
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asm::dsb(); |
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if ! self.regs.tx_status.read().tx_go() { |
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self.regs.net_ctrl.modify(|_, w| |
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w.start_tx(true) |
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