zynq::slcr: fix a bitfield index

that didn't solve our problems.
master
Astro 3 years ago
parent 6bee1f44f4
commit 04e816d99e
  1. 2
      src/zynq/slcr.rs

@ -376,7 +376,7 @@ register_bits!(gem_clk_ctrl,
divisor, u8, 8, 13);
register_bits_typed!(gem_clk_ctrl,
/// Source to generate the ref clock
srcsel, u8, PllSource, 4, 5);
srcsel, u8, PllSource, 4, 6);
register_bit!(gem_clk_ctrl,
/// SMC reference clock control
clkact, 0);

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