forked from M-Labs/zynq-rs
read clocks
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1f9ad5ff62
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b8818863c4
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@ -0,0 +1,92 @@
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use crate::slcr;
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use crate::regs::RegisterR;
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#[cfg(feature = "target_zc706")]
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const PS_CLK: u32 = 33_333_333;
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#[cfg(feature = "target_cora_z7_10")]
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const PS_CLK: u32 = 50_000_000;
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enum CpuClockMode {
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/// Clocks run in 4:2:2:1 mode
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C421,
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/// Clocks run in 6:3:2:1 mode
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C621,
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}
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impl CpuClockMode {
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pub fn get() -> Self {
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let regs = slcr::RegisterBlock::new();
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if regs.clk_621_true.read().clk_621_true() {
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CpuClockMode::C621
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} else {
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CpuClockMode::C421
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}
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}
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}
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#[derive(Debug, Clone)]
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pub struct CpuClocks {
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/// ARM PLL: Recommended clock source for the CPUs and the interconnect
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pub arm: u32,
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/// DDR PLL: Recommended clock for the DDR DRAM controller and AXI_HP interfaces
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pub ddr: u32,
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/// I/O PLL: Recommended clock for I/O peripherals
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pub io: u32,
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}
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impl CpuClocks {
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pub fn get() -> Self {
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let regs = slcr::RegisterBlock::new();
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let arm = u32::from(regs.arm_pll_ctrl.read().pll_fdiv()) * PS_CLK;
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let ddr = u32::from(regs.ddr_pll_ctrl.read().pll_fdiv()) * PS_CLK;
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let io = u32::from(regs.io_pll_ctrl.read().pll_fdiv()) * PS_CLK;
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CpuClocks { arm, ddr, io }
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}
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pub fn cpu_6x4x(&self) -> u32 {
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let regs = slcr::RegisterBlock::new();
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let arm_clk_ctrl = regs.arm_clk_ctrl.read();
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let pll = match arm_clk_ctrl.srcsel() {
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slcr::ArmPllSource::ArmPll => self.arm,
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slcr::ArmPllSource::DdrPll => self.ddr,
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slcr::ArmPllSource::IoPll => self.io,
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};
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pll / u32::from(arm_clk_ctrl.divisor())
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}
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pub fn cpu_3x2x(&self) -> u32 {
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self.cpu_6x4x() / 2
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}
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pub fn cpu_2x(&self) -> u32 {
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match CpuClockMode::get() {
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CpuClockMode::C421 =>
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self.cpu_6x4x() / 2,
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CpuClockMode::C621 =>
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self.cpu_6x4x() / 3,
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}
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}
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pub fn cpu_1x(&self) -> u32 {
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match CpuClockMode::get() {
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CpuClockMode::C421 =>
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self.cpu_6x4x() / 4,
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CpuClockMode::C621 =>
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self.cpu_6x4x() / 6,
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}
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}
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pub fn uart_ref_clk(&self) -> u32 {
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let regs = slcr::RegisterBlock::new();
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let uart_clk_ctrl = regs.uart_clk_ctrl.read();
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let pll = match uart_clk_ctrl.srcsel() {
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slcr::PllSource::ArmPll =>
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self.arm,
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slcr::PllSource::DdrPll =>
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self.ddr,
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slcr::PllSource::IoPll =>
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self.io,
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};
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pll / u32::from(uart_clk_ctrl.divisor())
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}
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}
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@ -1,6 +1,7 @@
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use crate::regs::*;
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use crate::slcr;
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use crate::println;
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use crate::clocks::CpuClocks;
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pub mod phy;
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mod regs;
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@ -9,7 +10,6 @@ pub mod tx;
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/// Size of all the buffers
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pub const MTU: usize = 1536;
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pub const IO_PLL: u32 = 1_000;
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pub struct Eth<RX, TX> {
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regs: &'static mut regs::RegisterBlock,
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@ -176,14 +176,15 @@ impl Eth<(), ()> {
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impl<RX, TX> Eth<RX, TX> {
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pub fn setup_gem0_clock(tx_clock: u32) {
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let d0 = (IO_PLL / tx_clock).min(63);
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let d1 = (IO_PLL / tx_clock / d0).min(63);
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let io_pll = CpuClocks::get().io;
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let d0 = (io_pll / tx_clock).min(63);
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let d1 = (io_pll / tx_clock / d0).min(63);
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.gem0_clk_ctrl.write(
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// 0x0050_0801: 8, 5: 100 Mb/s
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// ...: 8, 1: 1000 Mb/s
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slcr::ClkCtrl::zeroed()
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slcr::GemClkCtrl::zeroed()
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.clkact(true)
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.srcsel(slcr::PllSource::IoPll)
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.divisor(d0 as u8)
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@ -199,12 +200,13 @@ impl<RX, TX> Eth<RX, TX> {
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}
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pub fn setup_gem1_clock(tx_clock: u32) {
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let d0 = (IO_PLL / tx_clock).min(63);
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let d1 = (IO_PLL / tx_clock / d0).min(63);
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let io_pll = CpuClocks::get().io;
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let d0 = (io_pll / tx_clock).min(63);
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let d1 = (io_pll / tx_clock / d0).min(63);
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.gem1_clk_ctrl.write(
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slcr::ClkCtrl::zeroed()
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slcr::GemClkCtrl::zeroed()
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.clkact(true)
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.srcsel(slcr::PllSource::IoPll)
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.divisor(d0 as u8)
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@ -15,6 +15,7 @@ use compiler_builtins as _;
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mod regs;
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mod cortex_a9;
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mod clocks;
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mod slcr;
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mod uart;
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mod stdio;
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@ -74,6 +75,13 @@ fn l1_cache_init() {
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fn main() {
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println!("Main.");
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let clocks = clocks::CpuClocks::get();
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println!("Clocks: {:?}", clocks);
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println!("CPU speeds: {}/{}/{}/{} MHz",
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clocks.cpu_6x4x() / 1_000_000,
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clocks.cpu_3x2x() / 1_000_000,
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clocks.cpu_2x() / 1_000_000,
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clocks.cpu_1x() / 1_000_000);
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let mut eth = eth::Eth::default([0x0, 0x17, 0xde, 0xea, 0xbe, 0xef]);
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println!("Eth on");
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52
src/slcr.rs
52
src/slcr.rs
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@ -12,6 +12,13 @@ pub enum PllSource {
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DdrPll = 0b11,
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}
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#[repr(u8)]
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pub enum ArmPllSource {
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ArmPll = 0b00,
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DdrPll = 0b10,
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IoPll = 0b11,
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}
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#[repr(C)]
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pub struct RegisterBlock {
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pub scl: RW<u32>,
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@ -19,15 +26,15 @@ pub struct RegisterBlock {
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pub slcr_unlock: SlcrUnlock,
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pub slcr_locksta: RO<u32>,
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reserved0: [u32; 60],
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pub arm_pll_ctrl: RW<u32>,
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pub ddr_pll_ctrl: RW<u32>,
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pub io_pll_ctrl: RW<u32>,
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pub arm_pll_ctrl: PllCtrl,
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pub ddr_pll_ctrl: PllCtrl,
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pub io_pll_ctrl: PllCtrl,
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pub pll_status: RO<u32>,
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pub arm_pll_cfg: RW<u32>,
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pub ddr_pll_cfg: RW<u32>,
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pub io_pll_cfg: RW<u32>,
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reserved1: [u32; 1],
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pub arm_clk_ctrl: RW<u32>,
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pub arm_clk_ctrl: ArmClkCtrl,
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pub ddr_clk_ctrl: RW<u32>,
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pub dci_clk_ctrl: RW<u32>,
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pub aper_clk_ctrl: AperClkCtrl,
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@ -35,8 +42,8 @@ pub struct RegisterBlock {
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pub usb1_clk_ctrl: RW<u32>,
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pub gem0_rclk_ctrl: RclkCtrl,
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pub gem1_rclk_ctrl: RclkCtrl,
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pub gem0_clk_ctrl: ClkCtrl,
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pub gem1_clk_ctrl: ClkCtrl,
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pub gem0_clk_ctrl: GemClkCtrl,
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pub gem1_clk_ctrl: GemClkCtrl,
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pub smc_clk_ctrl: RW<u32>,
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pub lqspi_clk_ctrl: RW<u32>,
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pub sdio_clk_ctrl: RW<u32>,
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@ -64,7 +71,7 @@ pub struct RegisterBlock {
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pub fpga3_thr_cnt: RW<u32>,
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pub fpga3_thr_sta: RO<u32>,
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reserved2: [u32; 5],
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pub clk_621_true: RW<u32>,
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pub clk_621_true: Clk621True,
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reserved3: [u32; 14],
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pub pss_rst_ctrl: PssRstCtrl,
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pub ddr_rst_ctrl: RW<u32>,
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@ -239,6 +246,27 @@ impl SlcrUnlock {
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}
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}
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register!(pll_ctrl, PllCtrl, RW, u32);
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register_bits!(pll_ctrl, pll_fdiv, u8, 12, 18);
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register_bit!(pll_ctrl, pll_bypass_force, 4);
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register_bit!(pll_ctrl, pll_bypass_qual, 3);
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register_bit!(pll_ctrl, pll_pwrdwn, 1);
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register_bit!(pll_ctrl, pll_reset, 0);
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register!(arm_clk_ctrl, ArmClkCtrl, RW, u32);
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register_bit!(arm_clk_ctrl,
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/// Clock active
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cpu_peri_clkact, 28);
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register_bit!(arm_clk_ctrl, cpu_1xclkact, 27);
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register_bit!(arm_clk_ctrl, cpu_2xclkact, 26);
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register_bit!(arm_clk_ctrl, cpu_3or2xclkact, 25);
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register_bit!(arm_clk_ctrl, cpu_6or4xclkact, 24);
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register_bits!(arm_clk_ctrl, divisor, u8, 8, 13);
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register_bits_typed!(arm_clk_ctrl, srcsel, u8, ArmPllSource, 8, 13);
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register!(clk_621_true, Clk621True, RW, u32);
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register_bit!(clk_621_true, clk_621_true, 0);
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register!(aper_clk_ctrl, AperClkCtrl, RW, u32);
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register_bit!(aper_clk_ctrl, uart1_cpu_1xclkact, 21);
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register_bit!(aper_clk_ctrl, uart0_cpu_1xclkact, 20);
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@ -260,17 +288,17 @@ register_bit!(rclk_ctrl,
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/// false: MIO, true: EMIO
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srcsel, 4);
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register!(clk_ctrl, ClkCtrl, RW, u32);
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register_bits!(clk_ctrl,
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register!(gem_clk_ctrl, GemClkCtrl, RW, u32);
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register_bits!(gem_clk_ctrl,
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/// 2nd divisor for source clock
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divisor1, u8, 20, 25);
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register_bits!(clk_ctrl,
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register_bits!(gem_clk_ctrl,
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/// 1st divisor for source clock
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divisor, u8, 8, 13);
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register_bits_typed!(clk_ctrl,
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register_bits_typed!(gem_clk_ctrl,
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/// Source to generate the ref clock
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srcsel, u8, PllSource, 4, 5);
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register_bit!(clk_ctrl,
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register_bit!(gem_clk_ctrl,
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/// SMC reference clock control
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clkact, 0);
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@ -2,17 +2,11 @@ use core::fmt;
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use crate::regs::*;
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use crate::slcr;
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use crate::clocks::CpuClocks;
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mod regs;
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mod baud_rate_gen;
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/// Determined through experimentation. Actually supposed to be
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/// 1 GHz (IO PLL) / 0x14 (slcr.UART_CLK_CTRL[DIVISOR]) = 50 MHz.
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#[cfg(feature = "target_zc706")]
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const UART_REF_CLK: u32 = 50_000_000;
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#[cfg(feature = "target_cora_z7_10")]
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const UART_REF_CLK: u32 = 72_000_000;
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pub struct Uart {
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regs: &'static mut regs::RegisterBlock,
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}
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@ -116,7 +110,8 @@ impl Uart {
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self.disable_rx();
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self.disable_tx();
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baud_rate_gen::configure(self.regs, UART_REF_CLK, baudrate);
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let clocks = CpuClocks::get();
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baud_rate_gen::configure(self.regs, clocks.uart_ref_clk(), baudrate);
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// Enable controller
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self.reset_rx();
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