forked from M-Labs/zynq-rs
slcr: implement PllCfg and DdrClkCtrl
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parent
83b8bb096a
commit
58cf9833cc
19
src/slcr.rs
19
src/slcr.rs
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@ -30,12 +30,12 @@ pub struct RegisterBlock {
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pub ddr_pll_ctrl: PllCtrl,
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pub io_pll_ctrl: PllCtrl,
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pub pll_status: RO<u32>,
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pub arm_pll_cfg: RW<u32>,
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pub ddr_pll_cfg: RW<u32>,
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pub io_pll_cfg: RW<u32>,
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pub arm_pll_cfg: PllCfg,
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pub ddr_pll_cfg: PllCfg,
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pub io_pll_cfg: PllCfg,
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reserved1: [u32; 1],
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pub arm_clk_ctrl: ArmClkCtrl,
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pub ddr_clk_ctrl: RW<u32>,
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pub ddr_clk_ctrl: DdrClkCtrl,
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pub dci_clk_ctrl: RW<u32>,
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pub aper_clk_ctrl: AperClkCtrl,
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pub usb0_clk_ctrl: RW<u32>,
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@ -253,6 +253,11 @@ register_bit!(pll_ctrl, pll_bypass_qual, 3);
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register_bit!(pll_ctrl, pll_pwrdwn, 1);
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register_bit!(pll_ctrl, pll_reset, 0);
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register!(pll_cfg, PllCfg, RW, u32);
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register_bits!(pll_cfg, pll_res, u8, 4, 7);
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register_bits!(pll_cfg, pll_cp, u8, 8, 11);
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register_bits!(pll_cfg, lock_cnt, u16, 12, 21);
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register!(arm_clk_ctrl, ArmClkCtrl, RW, u32);
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register_bit!(arm_clk_ctrl,
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/// Clock active
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@ -264,6 +269,12 @@ register_bit!(arm_clk_ctrl, cpu_6or4xclkact, 24);
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register_bits!(arm_clk_ctrl, divisor, u8, 8, 13);
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register_bits_typed!(arm_clk_ctrl, srcsel, u8, ArmPllSource, 8, 13);
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register!(ddr_clk_ctrl, DdrClkCtrl, RW, u32);
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register_bit!(ddr_clk_ctrl, ddr_3xclkact, 0);
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register_bit!(ddr_clk_ctrl, ddr_2xclkact, 1);
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register_bits!(ddr_clk_ctrl, ddr_3xclk_divisor, u8, 20, 25);
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register_bits!(ddr_clk_ctrl, ddr_2xclk_divisor, u8, 26, 31);
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register!(clk_621_true, Clk621True, RW, u32);
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register_bit!(clk_621_true, clk_621_true, 0);
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