 Jack-Zheng
|
09ebd078c2
|
CurrentSenser: connect reference voltage to MCU ADC
|
2021-07-10 13:19:05 +08:00 |
|
Jack-Zheng
|
66d7d68a55
|
CurrentSense, HSADC: add decoupling caps; Power: add 3.3V output fuse; HSADC: add ESD protection; PCB: add logo
|
2021-07-09 20:18:06 +08:00 |
|
Jack-Zheng
|
3dd53b1fe4
|
PCB: refill polygon
|
2021-07-09 16:19:37 +08:00 |
|
Jack-Zheng
|
3a06817165
|
CurrentSense: connect FAULT signal to MCU
|
2021-07-09 16:07:40 +08:00 |
|
Jack-Zheng
|
191eacdf8c
|
HSADC: change from AC coupling to DC coupling; PCB: finish HSADC layout; LVDS&IO: fix name issue
|
2021-07-09 14:36:13 +08:00 |
|
Jack-Zheng
|
3228e16c8f
|
MCU, FPGA, Ethernet, PCB: fix decoupling capacitors
|
2021-07-07 16:14:10 +08:00 |
|
Jack-Zheng
|
90053d4887
|
PowerSupply: fix TVS protection bug; PCB: finish routing
|
2021-07-06 15:41:17 +08:00 |
|
Jack-Zheng
|
eceba52792
|
PCB & FPGA & MCU: fix LVDS impedance issues
|
2021-07-06 10:28:18 +08:00 |
|
Jack-Zheng
|
1b592eed37
|
FPGA & MCU & PCB: add decoupling capactors
|
2021-07-02 11:04:53 +08:00 |
|
Jack-Zheng
|
f796eedc08
|
PCB: fix grand dead zones
|
2021-06-30 15:24:25 +08:00 |
|
Jack-Zheng
|
4853b02184
|
PCB: replace 0201 resistors to 0402 as JLC cannot do SMT for 0201
|
2021-06-30 14:59:13 +08:00 |
|
Jack-Zheng
|
93ba0cbe9d
|
HSADC: change from AC coupling to DC coupling; PCB: finish HSADC layout
|
2021-06-30 14:51:30 +08:00 |
|
Jack-Zheng
|
17127387c9
|
PCB: optimize buck converter and shunt resistor layout
|
2021-06-30 11:36:53 +08:00 |
|
Jack-Zheng
|
26d727f8c5
|
PCB: replace LVDS resistors with 0201 package, optimize LVDS pairs layout
|
2021-06-29 16:49:26 +08:00 |
|
Jack-Zheng
|
8ffd698079
|
PCB: optimize HSADC layout
|
2021-06-29 10:38:12 +08:00 |
|
Jack-Zheng
|
6584f44f2a
|
PCB: fix GND polygon dead zones; all: export BOM
|
2021-06-29 10:26:02 +08:00 |
|
Jack-Zheng
|
10818a4771
|
PCB: fix small LVDS connection issue
|
2021-06-28 15:49:33 +08:00 |
|
Jack-Zheng
|
a16bee581b
|
PCB: fix small LVDS connection issue
|
2021-06-28 15:45:06 +08:00 |
|
Jack-Zheng
|
185f9eacda
|
PCB: finish routing
|
2021-06-28 15:40:16 +08:00 |
|
Jack-Zheng
|
53accc8761
|
PCB: finish IO and analog connectors
|
2021-06-28 10:40:21 +08:00 |
|
Jack-Zheng
|
4b15f466a0
|
PCB: finish SWD, IIC
|
2021-06-25 18:15:56 +08:00 |
|
Jack-Zheng
|
0e1120d266
|
FPGA: modify pin connections for convenient layout routing; PCB: finish FPGA IO, FSMC, ADC BUS, Power routing
|
2021-06-25 16:57:46 +08:00 |
|
Jack-Zheng
|
2a31c8b3f3
|
PCB: finish LVDS routing
|
2021-06-24 15:43:31 +08:00 |
|
Jack-Zheng
|
37941bfc2c
|
PCB: finalize component positions and define board shape
|
2021-06-22 17:14:32 +08:00 |
|
Jack-Zheng
|
6535ff5423
|
LVDS&IO: add fpga flash config; all: fix connection bugs; PCB: initialize component positions and layout
|
2021-06-22 16:34:02 +08:00 |
|
Jack-Zheng
|
1df738664f
|
all: update gitignore; remove redundant files
|
2021-06-22 09:44:50 +08:00 |
|
Jack-Zheng
|
982fefd6b5
|
all: update gitigore to fix symbol and footpin bugs; replace messy libs into one
|
2021-06-21 16:05:17 +08:00 |
|
Jack-Zheng
|
9bcc9a229b
|
TestAutomation: replace messy wires with bus
|
2021-06-21 12:10:31 +08:00 |
|
Jack-Zheng
|
dfe4255a21
|
MCU: finish FSMC, PWM
|
2021-06-17 10:52:33 +08:00 |
|
Jack-Zheng
|
5b4801ff74
|
FPGA: finish EEM, I2C, CFG, SPI FLASH
|
2021-06-16 17:32:33 +08:00 |
|
Jack-Zheng
|
fc2cb47610
|
all: map symbol and footpins
|
2021-06-16 17:32:33 +08:00 |
|
Jack-Zheng
|
da19dad9cd
|
init project
|
2021-06-16 17:31:36 +08:00 |