94c4f8e6f7
hitl: undo bin change to make merging easier
2021-01-20 15:09:50 +01:00
2236e5f8ab
Merge remote-tracking branch 'origin/master' into hitl
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* origin/master: (34 commits)
Reordering lib.rs
Removing main.rs
Adding support for multiple applications
Fixing build
Moving panic configuration
Reordering
Refactoring to support multiple apps
Updating timer compare offsets
reciprocal_pll: remove unneeded type cast
revert changes in main.rs and server.rs
dsp: add reciprocal_pll
fix bug in which real signal component is assigned twice
fix cargo fmt style
use only integer iir
remove TODO note relating ADC_BATCHES and calculate_timestamp_timer_period
shift sin/cos before demodulation product to avoid i64
use round up half integer rounding
move timestamp handling into new TimestampHandler struct
move lock-in code to main.rs
remove debug_assert in divide_round
...
2021-01-20 15:08:47 +01:00
a31c9a5a7a
Merge pull request #234 from vertigo-designs/feature/multi-app-support
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Feature/multi app support
2021-01-20 14:09:47 +01:00
4d0b1b5566
Reordering lib.rs
2021-01-20 13:44:53 +01:00
86355c9c5d
Removing main.rs
2021-01-20 13:44:16 +01:00
26677063ea
Adding support for multiple applications
2021-01-20 13:43:34 +01:00
Ryan Summers
058e474b78
Merge pull request #230 from vertigo-designs/feature/hardware-module
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Refactoring to support multiple apps
2021-01-20 12:35:36 +01:00
573189bdd9
Fixing build
2021-01-18 17:23:21 +01:00
6618e921fe
Moving panic configuration
2021-01-18 16:55:56 +01:00
8dd72ae75e
Reordering
2021-01-18 16:52:09 +01:00
20535a721d
Refactoring to support multiple apps
2021-01-18 16:47:47 +01:00
Ryan Summers
d447501c47
Merge pull request #208 from vertigo-designs/feature/io-docs
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Adding documentation, updating DAC output timing
2021-01-18 13:54:56 +01:00
7a2f950667
Updating timer compare offsets
2021-01-18 13:41:23 +01:00
598a48b178
Merge branch 'master' into feature/io-docs
2021-01-18 13:25:03 +01:00
1d0e1f9651
Merge pull request #222 from matthuszagh/lockin
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Lockin
2021-01-13 18:47:37 +01:00
Matt Huszagh
9697560404
reciprocal_pll: remove unneeded type cast
2021-01-13 09:08:16 -08:00
Matt Huszagh
e599977983
revert changes in main.rs and server.rs
2021-01-13 08:59:27 -08:00
Matt Huszagh
76088efda5
dsp: add reciprocal_pll
2021-01-13 08:37:33 -08:00
Matt Huszagh
6aad92af43
fix bug in which real signal component is assigned twice
2021-01-12 18:36:18 -08:00
Matt Huszagh
07b7201b49
fix cargo fmt style
2021-01-12 17:26:42 -08:00
Matt Huszagh
a0d472b398
use only integer iir
2021-01-12 17:21:55 -08:00
Matt Huszagh
f974f4099c
remove TODO note relating ADC_BATCHES and calculate_timestamp_timer_period
...
Having both is not really redundant.
2021-01-12 16:17:58 -08:00
Matt Huszagh
80ed715f5a
shift sin/cos before demodulation product to avoid i64
2021-01-12 16:07:04 -08:00
Matt Huszagh
41ea2ebed4
use round up half integer rounding
2021-01-12 15:59:03 -08:00
Matt Huszagh
4c033c0f3e
move timestamp handling into new TimestampHandler struct
2021-01-12 13:06:49 -08:00
Matt Huszagh
e14aa8b613
move lock-in code to main.rs
2021-01-12 10:45:34 -08:00
184a343a7a
hitl: dispatch entire github object
2021-01-12 19:06:47 +01:00
Matt Huszagh
891aad3f17
remove debug_assert in divide_round
2021-01-12 07:43:28 -08:00
Matt Huszagh
31d23a3e0c
lock-in: use same method for batch_index branching in both instances
2021-01-12 07:36:56 -08:00
Matt Huszagh
bae295140d
update lock-in for integer math and PLL
2021-01-12 07:36:56 -08:00
Matt Huszagh
028f4a1bb2
fix small typos
2021-01-12 07:36:56 -08:00
Ryan Summers
ad3681f30b
Merge pull request #223 from quartiq/rs/issue-219/adc-setup
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Conforming to external ADC conversion timing
2021-01-12 07:05:17 -08:00
Ryan Summers
db3a42a7b9
Update src/adc.rs
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Co-authored-by: Robert Jördens <rj@quartiq.de>
2021-01-12 06:54:16 -08:00
bcf7a59993
Removing dac isr clear
2021-01-12 14:15:45 +01:00
09ecd3291a
Merge branch 'rs/issue-219/adc-setup' into feature/io-docs
2021-01-12 14:02:19 +01:00
6b170c25ed
Fixing timing synchronization
2021-01-12 13:29:15 +01:00
91975993cf
Fixing docs
2021-01-11 12:38:20 +01:00
d5c21efc9d
Adding extra DMA transfer to clear TXTF in ADC SPI transfers
2021-01-11 12:31:15 +01:00
Ryan Summers
1307ddb0ba
Merge pull request #196 from vertigo-designs/feature/pounder-timestamping
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Feature/pounder timestamping
2021-01-11 01:50:09 -08:00
f785ec2f51
hitl: dispatch stabilizer event
2021-01-08 19:13:48 +01:00
09a7ab2773
ci: correctly use stable toolchain
2021-01-08 19:09:42 +01:00
96dc13da35
hitl: rename, add badge
2021-01-08 19:05:51 +01:00
5ecb28fb05
Merge pull request #220 from quartiq/jordens-hitl
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hardware in the loop testing
2021-01-08 17:30:12 +01:00
72d69960ca
Create hitl.yml
2021-01-08 17:28:07 +01:00
5eab732d93
Adding information about DSP timing specifications
2021-01-06 15:38:04 +01:00
56366a013f
Specifying consequences of failing to meet timing
2021-01-06 15:34:12 +01:00
f6062c666e
Fixing pounder v1.1 build
2021-01-06 15:13:28 +01:00
4b3ceb0c0b
Merge branch 'feature/io-docs' of github.com:vertigo-designs/stabilizer into feature/io-docs
2021-01-06 15:12:25 +01:00
eefb2acfda
Updating dependencies
2021-01-06 15:12:03 +01:00
cd4721b506
Merge branch 'master' into feature/io-docs
2021-01-06 15:10:30 +01:00
