dsleung

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• Joined on 2020-05-28

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dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-27 12:31:06 +08:00

472e0a70f8 Update README.md

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-27 12:28:29 +08:00

94da2671dc Add LD instruction

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-27 12:25:29 +08:00

bd76a47a52 Add LWU instruction

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-27 12:20:28 +08:00

92e34efe0d Add RV64I I-Type Instruction (Load Variation)

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-27 11:46:15 +08:00

0af1f20423 Add RV64I I-Type Instruction

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-27 10:48:45 +08:00

fe835e272d Replace RV32I with RV32M for Minerva verification tasks

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-27 10:33:01 +08:00

1ea25a4886 Add RV32M Standard Extension

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-26 17:21:36 +08:00

3f3ec597a1 Update README.md

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-26 17:15:36 +08:00

46e6ca3f70 Add REMU instruction

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-26 17:11:13 +08:00

fb91df7bb8 Add REM instruction

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-26 17:04:02 +08:00

33ace9147a Add DIVU instruction

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-26 16:58:57 +08:00

0708f6b962 Add DIV instruction

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-26 16:43:30 +08:00

b74a0cf699 Add MULHU instruction

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-26 16:39:29 +08:00

a58842ea94 Add MULHSU instruction

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-26 16:31:03 +08:00

15580a74c6 Add MULH instruction

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-26 15:57:46 +08:00

585965ee0a Add MUL instruction

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-26 15:49:09 +08:00

dd17606902 Add RV32M R-Type Instruction

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-25 13:38:41 +08:00

3030839c42 Update README.md

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-25 13:17:25 +08:00

d1d93a6b6a Update README.md

dsleung pushed to master at M-Labs/riscv-formal-nmigen 2020-08-25 12:43:22 +08:00

83e65e50c5 Fix broken README