.. | ||
__init__.py | ||
insn_add.py | ||
insn_addi.py | ||
insn_addiw.py | ||
insn_addw.py | ||
insn_and.py | ||
insn_andi.py | ||
insn_auipc.py | ||
insn_beq.py | ||
insn_bge.py | ||
insn_bgeu.py | ||
insn_blt.py | ||
insn_bltu.py | ||
insn_bne.py | ||
insn_div.py | ||
insn_divu.py | ||
insn_jal.py | ||
insn_jalr.py | ||
insn_lb.py | ||
insn_lbu.py | ||
insn_ld.py | ||
insn_lh.py | ||
insn_lhu.py | ||
insn_lui.py | ||
insn_lw.py | ||
insn_lwu.py | ||
insn_mul.py | ||
insn_mulh.py | ||
insn_mulhsu.py | ||
insn_mulhu.py | ||
insn_mulw.py | ||
insn_or.py | ||
insn_ori.py | ||
insn_rem.py | ||
insn_remu.py | ||
insn_rv32i_i_type_arith.py | ||
insn_rv32i_i_type_load.py | ||
insn_rv32i_i_type_shift.py | ||
insn_rv32i_i_type.py | ||
insn_rv32i_r_type.py | ||
insn_rv32i_s_type.py | ||
insn_rv32i_sb_type.py | ||
insn_rv32i_u_type.py | ||
insn_rv32m_r_type.py | ||
insn_rv64i_i_type_load.py | ||
insn_rv64i_i_type_shift.py | ||
insn_rv64i_i_type.py | ||
insn_rv64i_r_type.py | ||
insn_rv64m_r_type.py | ||
insn_sb.py | ||
insn_sd.py | ||
insn_sh.py | ||
insn_sll.py | ||
insn_slli.py | ||
insn_slliw.py | ||
insn_sllw.py | ||
insn_slt.py | ||
insn_slti.py | ||
insn_sltiu.py | ||
insn_sltu.py | ||
insn_sra.py | ||
insn_srai.py | ||
insn_sraiw.py | ||
insn_sraw.py | ||
insn_srl.py | ||
insn_srli.py | ||
insn_srliw.py | ||
insn_srlw.py | ||
insn_sub.py | ||
insn_subw.py | ||
insn_sw.py | ||
insn_xor.py | ||
insn_xori.py | ||
insn.py | ||
isa_rv32i.py | ||
isa_rv32m.py | ||
isa_rv64i.py | ||
README.md |
RISC-V Instructions
Instructions
Below is a table of RISC-V instructions supported by the original riscv-formal framework at the time of writing, categorized by instruction type.
Instruction type | Instructions |
---|---|
R-type | ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR |
I-type | ADDI, ADDIW, ANDI, JALR, LB, LBU, LD, LH, LHU, LW, LWU, ORI, SLTI, SLTIU, XORI |
I-type (shift variation) | SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW |
S-type | SB, SD, SH, SW |
SB-type | BEQ, BGE, BGEU, BLT, BLTU, BNE |
U-type | AUIPC, LUI |
UJ-type | JAL |
CI-type | C_ADD, C_ADDI, C_ADDIW, C_JALR, C_JR, C_LI, C_MV |
CI-type (SP variation) | C_ADDI16SP |
CI-type (ANDI variation) | C_ANDI |
CI-type (LSP variation, 32 bit version) | C_LWSP |
CI-type (LSP variation, 64 bit version) | C_LDSP |
CI-type (LUI variation) | C_LUI |
CI-type (SLI variation) | C_SLLI |
CI-type (SRI variation) | C_SRAI, C_SRLI |
CIW-type | C_ADDI4SPN |
CS-type (ALU version) | C_ADDW, C_AND, C_OR, C_SUB, C_SUBW, C_XOR |
CS-type (32 bit version) | C_SW |
CS-type (64 bit version) | C_SD |
CSS-type (32 bit version) | C_SWSP |
CSS-type (64 bit version) | C_SDSP |
CB-type | C_BEQZ, C_BNEZ |
CJ-type | C_J, C_JAL |
CL-type (32 bit version) | C_LW |
CL-type (64 bit version) | C_LD |
Class Synopsis
Instructions
Below is a list of instructions currently supported by this port of the riscv-formal framework and is expected to grow over time. The instructions are roughly grouped by instruction type but sometimes with further specializations - the hierarchy of the lists reflects the hierarchy of inheritance in the classes used to represent various instructions.
Insn
: General RISC-V instructionInsnRV32IRType
: RV32I R-Type InstructionInsnAdd
: ADD instructionInsnSub
: SUB instructionInsnSll
: SLL instructionInsnSlt
: SLT instructionInsnSltu
: SLTU instructionInsnXor
: XOR instructionInsnSrl
: SRL instructionInsnSra
: SRA instructionInsnOr
: OR instructionInsnAnd
: AND instruction
InsnRV32IITypeShift
: RV32I I-Type Instruction (Shift Variation)InsnSlli
: SLLI instructionInsnSrli
: SRLI instructionInsnSrai
: SRAI instruction
InsnRV32IIType
: RV32I I-Type InstructionInsnJalr
: JALR instructionInsnRV32IITypeLoad
: RV32I I-Type Instruction (Load Variation)InsnLb
: LB instructionInsnLh
: LH instructionInsnLw
: LW instructionInsnLbu
: LBU instructionInsnLhu
: LHU instruction
InsnRV32IITypeArith
: RV32I I-Type Instruction (Arithmetic Variation)InsnAddi
: ADDI instructionInsnSlti
: SLTI instructionInsnSltiu
: SLTIU instructionInsnXori
: XORI instructionInsnOri
: ORI instructionInsnAndi
: ANDI instruction
InsnRV32ISType
: RV32I S-Type InstructionInsnSb
: SB instructionInsnSh
: SH instructionInsnSw
: SW instruction
InsnRV32ISBType
: RV32I SB-Type InstructionInsnBeq
: BEQ instructionInsnBne
: BNE instructionInsnBlt
: BLT instructionInsnBge
: BGE instructionInsnBltu
: BLTU instructionInsnBgeu
: BGEU instruction
InsnJal
: JAL instructionInsnRV32IUType
: RV32I U-Type InstructionInsnLui
: LUI instructionInsnAuipc
: AUIPC instruction
InsnRV32MRType
: RV32M R-Type InstructionInsnMul
: MUL instructionInsnMulh
: MULH instructionInsnMulhsu
: MULHSU instructionInsnMulhu
: MULHU instructionInsnDiv
: DIV instructionInsnDivu
: DIVU instructionInsnRem
: REM instructionInsnRemu
: REMU instruction
InsnRV64IIType
: RV64I I-Type InstructionInsnRV64IITypeLoad
: RV64I I-Type Instruction (Load Variation)InsnLwu
: LWU instructionInsnLd
: LD instruction
InsnAddiw
: ADDIW instructionInsnRV64IITypeShift
: RV64I I-Type Instruction (Shift Variation)InsnSlliw
: SLLIW instructionInsnSrliw
: SRLIW instructionInsnSraiw
: SRAIW instruction
InsnRV64IRType
: RV64I R-Type InstructionInsnAddw
: ADDW instructionInsnSubw
: SUBW instructionInsnSllw
: SLLW instructionInsnSrlw
: SRLW instructionInsnSraw
: SRAW instruction
InsnSd
: SD instruction
ISAs
IsaRV32I
: RV32I Base ISAIsaRV32M
: RV32M Standard ExtensionIsaRV64I
: RV64I Base ISA
Core-specific parameters
The following core-specific parameters are currently supported:
Parameter | Description | Valid value(s) |
---|---|---|
params.ilen |
Max length of instruction retired by core | 32 |
params.xlen |
Width of integer registers | 32 |
params.csr_misa |
Support for MISA CSRs enabled | True , False |
params.compressed |
Support for compressed instructions | True , False |
params.aligned_mem |
Require aligned memory accesses | True , False |
params.altops |
Use alternative operations for multiplication/division | True , False |