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mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 19:28:26 +08:00
Commit Graph

140 Commits

Author SHA1 Message Date
fb75bd246e targets/kc705: make AMP the default 2015-04-11 17:16:25 +08:00
b492aad1c4 targets/kc705: enable Ethernet core 2015-04-10 13:15:32 +08:00
cb2596bd81 coredevice/comm: split protocol to allow reuse for Ethernet 2015-04-10 00:59:35 +08:00
44304a33b2 soc,runtime: define RTIO FUD channel number in targets 2015-04-09 00:35:11 +08:00
7e591bb1c7 targets: use _Peripherals/UP/AMP class names, share QC1 IO defs 2015-04-07 00:07:53 +08:00
5538ad5c70 runtime: support RPC exceptions on AMP 2015-04-06 22:28:10 +08:00
45bb9d8840 runtime: support RPC and log on AMP 2015-04-06 19:40:12 +08:00
f26c53cb35 runtime: use KERNELCPU_PAYLOAD_ADDRESS on UP 2015-04-05 22:16:51 +08:00
0c62f0f69c runtime: remove generated service_table.h 2015-04-05 22:08:20 +08:00
72f9f7ed79 runtime: implement mailbox, use it for kernel startup, exceptions and termination 2015-04-05 22:07:34 +08:00
1bca614d11 runtime: use UP/AMP terminology 2015-04-05 17:55:05 +08:00
ef375b5c9c pipistrello: add double-cpu 2015-04-04 20:52:08 -06:00
afc3982555 pipistrello: refactor single-cpu 2015-04-04 20:51:47 -06:00
0ae4492077 pipistrello: use mem_decoder 2015-04-04 20:51:47 -06:00
e50661dac4 pipistrello: fix dcm parameters, move leds, fix names 2015-04-04 20:51:47 -06:00
cbdc1ba46f runtime: biprocessor support (incomplete, WIP) 2015-04-04 22:08:32 +08:00
277e038569 targets/kc705: add LED on RTIO 2015-04-04 22:07:23 +08:00
21a0919ddc runtime: load support code into kernel CPU 2015-04-03 17:44:56 +08:00
c6d3750076 runtime,amp: set kernel memory start to SDRAM+128K, use custom linker file to split memory 2015-04-03 16:03:38 +08:00
5f7161a7de kc705: 16 TTLs 2015-04-03 15:57:25 +08:00
Florent Kermarrec
2995f0a705 remove use of _r prefix on CSRs 2015-04-02 18:30:44 +08:00
88a1707ef9 soc: use new location of gpio module 2015-04-02 17:19:00 +08:00
f124350555 runtime: disable kernel-CPU functions when kernel-CPU not present 2015-04-02 17:00:59 +08:00
4b66e3108a runtime: demonstrate basic inter-CPU communication 2015-04-02 16:54:08 +08:00
5fd7f68f48 targets/kc705: dual-CPU design 2015-04-02 16:53:57 +08:00
Yann Sionneau
e9092edb98 Remove one RTIO out channel to free up some space for travis builds to succeed 2015-03-30 19:51:52 +08:00
Florent Kermarrec
494c670cd2 targets/artiq_ppro: use new sdram_controller_settings parameter 2015-03-21 23:19:16 +01:00
fdca0a71ff add ARTIQMidiSoC based on pipistrello 2015-03-19 11:37:15 -06:00
7a1d60ee15 coredevice,runtime,language: add parameters to runtime exceptions, include information with RTIO errors 2015-03-13 14:55:18 +01:00
0416da8634 runtime/test: implement ttlout, clksel and dds functions 2015-03-12 13:14:06 +01:00
3122623c6f rtio: make 63-bit timestamp counter the default [soc] 2015-03-12 13:13:35 +01:00
d38014b07d soc/runtime: import DDS/TTL tester (functions not accessible yet) 2015-03-11 22:02:19 +01:00
28bce9ee40 artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
15d09c0b94 runtime: use new uart tuning word function 2015-03-02 23:36:05 +00:00
4e5320be28 Merge branch 'master' of https://github.com/m-labs/artiq 2015-02-28 07:34:38 -07:00
Florent Kermarrec
9cf8db2f14 adapt code to MiSoC's changes 2015-02-28 07:34:11 -07:00
7028d85255 targets/ppro: disable L2 2015-02-27 18:02:21 -07:00
Joe Britton
0127de9bb5 soc: add_cpu_csr_region -> add_csr_region 2015-02-27 15:02:28 -07:00
61f33a9a04 soc/ad9858: do not put code in __init__.py 2015-02-26 23:31:43 -07:00
da917f768e initial kc705 support 2015-02-26 21:50:52 -07:00
f7232fd3d1 support exceptions raised by RPCs 2014-12-20 21:33:22 +08:00
0d10ae7580 rpc: support all data types as parameters 2014-12-19 12:46:24 +08:00
059608d1fd dds: fix phase modes 2014-12-09 13:50:33 +08:00
fc690ead75 runtime: support clock switching 2014-12-02 14:06:32 +08:00
94218f785e comm_serial: cleanup 2014-12-02 11:09:02 +08:00
Yann Sionneau
20adb57140 comm_serial: allow to use dynamic baudrate 2014-12-02 10:42:14 +08:00
c591f1a74d targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG 2014-12-01 18:53:29 +08:00
cd587e4f12 rtio: do housekeeping in gateware 2014-12-01 17:32:36 +08:00
99d530e498 targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA 2014-12-01 17:31:35 +08:00
50e0bf3280 rtio: optimize flag handling 2014-12-01 14:29:50 +08:00