Drew
d60b95f481
tdr.py: typo ( #1220 )
2018-12-18 18:47:09 +00:00
a7d4d3bda9
ad9910: CONT_RECIRCULATE -> CONT_RAMPUP
2018-12-17 13:25:00 +00:00
35bdf26f01
Merge branch 'ad9910-ram'
2018-12-17 21:16:44 +08:00
David Nadlinger
e608d6ffd3
coredevice, firmware: Add rtio_input_timestamped_data
...
Integration tests to follow as part of an RTIO counter phy that
makes use of this.
2018-12-15 00:35:04 +00:00
David Nadlinger
8e30c4574b
firmware: Treat timestamps consistently as signed [nfc]
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This matches other functions and the ARTIQ Python side, but
isn't actually an ABI change.
2018-12-15 00:02:18 +00:00
38ce7ab8ff
sync_struct: handle TimeoutError as subscriber disconnection. Closes #1215
2018-12-13 06:58:54 +08:00
c09ab8502c
nix: cleanup
2018-12-13 06:57:10 +08:00
Joachim Schiele
73941d4661
nix: add rustc, migen and misoc
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This allows firmware compilation.
2018-12-12 22:24:55 +00:00
79eadb9465
ad9910: add RAM mode methods
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* also refactor the CFR1 access into a method
c.f. #1154
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 14:54:16 +00:00
6df4ae934f
eem: name the servo submodule
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This allows the migen namer to derive names for the ADC return clock
domain in the case of multiple SUServos
close #1201
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 11:36:40 +01:00
efd400b02c
ad9910: style [nfc]
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 11:36:25 +01:00
David Nadlinger
d4c393b2a8
firmware/ksupport: Update cfg(not(has_rtio)) stub signatures
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This fixes up 8caea0e6d3
2018-12-11 01:22:48 +00:00
d90eb3ae88
ad9910: add read64()
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-07 21:27:00 +00:00
baf88050fd
urukul: expand attenuator HITL unittests
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* read back with cleared backing state
* individual channel settings
* check backing state
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-07 21:06:12 +00:00
Kaifeng
cc143d5fec
kasli_tester: add support for windows platform. ( #1204 )
2018-12-05 14:06:45 +01:00
6aa341bc44
test_loopback_gate_timing: fix lat_offset
2018-12-02 20:52:32 +08:00
421834fa3e
compiler: document Target.little_endian
2018-12-02 19:07:18 +08:00
981a77834a
compiler: use default triple to determine data_layout for JIT
2018-12-02 18:52:13 +08:00
d931967e5c
fix previous commits
2018-12-02 18:32:03 +08:00
dd03fdfd1a
typo
2018-12-02 18:26:54 +08:00
8940009e1a
compiler: pass data_layout string to llvm.create_target_data before determining endianness
2018-12-02 18:26:19 +08:00
2e66788c6c
compiler: support little endian target when storing now
2018-12-02 17:40:34 +08:00
ad39c76a56
conda: fix llvmlite dependency
2018-12-02 06:40:00 +08:00
7e14f3ca4e
compiler,gateware: atomic now stores
2018-12-02 05:06:46 +08:00
fd00021a52
ctlmgr: do not raise exceptions in Controllers.__setitem__. Closes #1198
2018-12-01 18:09:58 +08:00
7f55376c75
test_loopback_gate_timing: print input timing for debugging
2018-12-01 18:09:53 +08:00
dce4f036db
grabber: work around windows numpy int peculiarity (same as a81c12de9)
2018-11-30 18:41:14 +08:00
156afb48ee
language: fix syscall arg handling
2018-11-30 17:59:24 +08:00
Paweł K
57caa7b149
artiq_flash: add command to erase flash memory ( #1197 )
2018-11-28 12:33:32 +02:00
3fd95b86c2
typo
2018-11-26 17:54:55 +08:00
5c162ed5e6
manual: document usage of DRTIO switching. Closes #1156
2018-11-26 17:53:28 +08:00
0507101e31
manual/drtio: update output internal description (SED, 'destination' switching terminology)
2018-11-26 16:50:09 +08:00
c56c0ba41f
rtio/dds: use write-only RT2WB
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This saves one address bit and prevents issues with AD9914 and 8-bit addresses.
2018-11-26 07:38:15 +08:00
09141e5bee
rtio/wishbone: support write-only interface
2018-11-26 07:38:06 +08:00
450a035f9e
suservo: move overflowing RTIO address bits into data
2018-11-26 06:54:20 +08:00
ae8ef18f47
rtlink: sanity-check parameters
2018-11-26 01:14:02 +08:00
b32e89444c
Merge branch 'master' into new
2018-11-26 01:02:19 +08:00
af9ea1f324
gui: update background
2018-11-26 01:01:36 +08:00
a81c12de94
urukul: work around windows numpy int peculiarity
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"OverflowError: Python int too large to convert to C long" otherwise
opticlock#74
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-25 16:56:45 +01:00
58ea111b8b
create 5.0.dev
2018-11-20 18:40:12 +08:00
bf50dcf76d
conda: use misoc release
2018-11-20 17:15:53 +08:00
8f9858be4c
ad9914: remove automatic continuous phase compensation (like Urukul)
2018-11-19 22:00:20 +08:00
22a223bf82
examples/master: clean up remnants of early urukul tests
2018-11-19 21:42:41 +08:00
f5befba5c9
conda: bump misoc (attempt to WA conda problem)
2018-11-19 13:24:28 +08:00
53e79f553f
Merge branch 'master' into new
2018-11-19 11:54:50 +08:00
b5cdb1c1e0
try to work around conda problem
2018-11-18 22:32:17 +08:00
a3e0b1c5b4
ad9914,spi2: add warnings about driver state and DMA. Closes #1113
2018-11-17 22:10:20 +08:00
78d4b3a7da
gateware/targets: expose variant lists
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This allows writing scripts that build all variants.
2018-11-17 22:10:20 +08:00
69e699c7bd
ttl: compensate for SED latency in input gating
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Closes #1137
2018-11-17 22:10:20 +08:00
3ad68f65c5
urukul: make get_att_mu() not alter state
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-16 14:56:26 +00:00
