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Sebastien Bourdeauducq 2018-11-26 01:02:19 +08:00
commit b32e89444c
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13
RELEASE_NOTES.rst
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@ -3,6 +3,14 @@
Release notes
=============
ARTIQ-5
-------
5.0
***
ARTIQ-4
-------
@ -67,6 +75,11 @@ ARTIQ-4
clocks dynamically (i.e. without device restart) is no longer supported.
* ``set_dataset(..., save=True)`` has been renamed
``set_dataset(..., archive=True)``.
* On the AD9914 DDS, when switching to ``PHASE_MODE_CONTINUOUS`` from another mode,
use the returned value of the last ``set_mu`` call as the phase offset for
``PHASE_MODE_CONTINUOUS`` to avoid a phase discontinuity. This is no longer done
automatically. If one phase glitch when entering ``PHASE_MODE_CONTINUOUS`` is not
an issue, this recommendation can be ignored.
ARTIQ-3

20
artiq/coredevice/ad9914.py
View File

@ -80,8 +80,6 @@ class AD9914:
self.set_x_duration_mu = 7 * self.write_duration_mu
self.exit_x_duration_mu = 3 * self.write_duration_mu
self.continuous_phase_comp = 0
@kernel
def write(self, addr, data):
rtio_output((self.bus_channel << 8) | addr, data)
@ -194,18 +192,16 @@ class AD9914:
The "frequency update" pulse is sent to the DDS with a fixed latency
with respect to the current position of the time cursor.
When switching from other phase modes to the continuous phase mode,
there is no jump in the DDS phase. This is however not true when
using the continuous phase mode after playing back a DMA sequence
that contained the other phase modes.
:param ftw: frequency to generate.
:param pow: adds an offset to the phase.
:param phase_mode: if specified, overrides the default phase mode set
by :meth:`set_phase_mode` for this call.
:param ref_time: reference time used to compute phase. Specifying this
makes it easier to have a well-defined phase relationship between
DDSes on the same bus that are updated at a similar time.
DDSes on the same bus that are updated at a similar time.
:return: Resulting phase offset word after application of phase
tracking offset. When using :const:`PHASE_MODE_CONTINUOUS` in
subsequent calls, use this value as the "current" phase.
"""
if phase_mode == _PHASE_MODE_DEFAULT:
phase_mode = self.phase_mode
@ -224,7 +220,6 @@ class AD9914:
# Do not clear phase accumulator on FUD
# Disable autoclear phase accumulator and enables OSK.
self.write(AD9914_REG_CFR1L, 0x0108)
pow += self.continuous_phase_comp
else:
# Clear phase accumulator on FUD
# Enable autoclear phase accumulator and enables OSK.
@ -233,11 +228,11 @@ class AD9914:
pow -= int32((ref_time - fud_time) * self.sysclk_per_mu * ftw >> (32 - 16))
if phase_mode == PHASE_MODE_TRACKING:
pow += int32(ref_time * self.sysclk_per_mu * ftw >> (32 - 16))
self.continuous_phase_comp = pow
self.write(AD9914_REG_POW, pow)
self.write(AD9914_REG_ASF, asf)
self.write(AD9914_FUD, 0)
return pow
@portable(flags={"fast-math"})
def frequency_to_ftw(self, frequency):
@ -280,9 +275,10 @@ class AD9914:
def set(self, frequency, phase=0.0, phase_mode=_PHASE_MODE_DEFAULT,
amplitude=1.0):
"""Like :meth:`set_mu`, but uses Hz and turns."""
self.set_mu(self.frequency_to_ftw(frequency),
return self.pow_to_turns(
self.set_mu(self.frequency_to_ftw(frequency),
self.turns_to_pow(phase), phase_mode,
self.amplitude_to_asf(amplitude))
self.amplitude_to_asf(amplitude)))
# Extended-resolution functions
@kernel

4
artiq/coredevice/urukul.py
View File

@ -1,7 +1,7 @@
from artiq.language.core import kernel, delay, portable, at_mu, now_mu
from artiq.language.units import us, ms
from numpy import int32
from numpy import int32, int64
from artiq.coredevice import spi2 as spi
@ -175,7 +175,7 @@ class CPLD:
self.cfg_reg = urukul_cfg(rf_sw=rf_sw, led=0, profile=0,
io_update=0, mask_nu=0, clk_sel=clk_sel,
sync_sel=sync_sel, rst=0, io_rst=0)
self.att_reg = int32(att)
self.att_reg = int32(int64(att))
self.sync_div = sync_div
@kernel

192
artiq/examples/master/device_db.py
View File

@ -120,34 +120,6 @@ device_db = {
"arguments": {"channel": 26}
},
# FMC DIO used to connect to Zotino
"fmcdio_dirctl_clk": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 27}
},
"fmcdio_dirctl_ser": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 28}
},
"fmcdio_dirctl_latch": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 29}
},
"fmcdio_dirctl": {
"type": "local",
"module": "artiq.coredevice.shiftreg",
"class": "ShiftReg",
"arguments": {"clk": "fmcdio_dirctl_clk",
"ser": "fmcdio_dirctl_ser",
"latch": "fmcdio_dirctl_latch"}
},
# DAC
"spi_ams101": {
"type": "local",
@ -161,184 +133,26 @@ device_db = {
"class": "TTLOut",
"arguments": {"channel": 20}
},
"spi_zotino": {
"type": "local",
"module": "artiq.coredevice.spi2",
"class": "SPIMaster",
"arguments": {"channel": 30}
},
"ttl_zotino_ldac": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 31}
},
"dac_zotino": {
"type": "local",
"module": "artiq.coredevice.zotino",
"class": "Zotino",
"arguments": {
"spi_device": "spi_zotino",
"ldac_device": "ttl_zotino_ldac",
"div_write": 30,
"div_read": 40
}
},
"spi_urukul": {
"type": "local",
"module": "artiq.coredevice.spi2",
"class": "SPIMaster",
"arguments": {"channel": 32}
},
"ttl_urukul_io_update": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 33}
},
"ttl_urukul_sw0": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 35}
},
"ttl_urukul_sw1": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 36}
},
"ttl_urukul_sw2": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 37}
},
"ttl_urukul_sw3": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 38}
},
"urukul_cpld": {
"type": "local",
"module": "artiq.coredevice.urukul",
"class": "CPLD",
"arguments": {
"spi_device": "spi_urukul",
"io_update_device": "ttl_urukul_io_update",
"refclk": 100e6
}
},
"urukul_ch0a": {
"type": "local",
"module": "artiq.coredevice.ad9912",
"class": "AD9912",
"arguments": {
"pll_n": 10,
"chip_select": 4,
"cpld_device": "urukul_cpld",
"sw_device": "ttl_urukul_sw0"
}
},
"urukul_ch1a": {
"type": "local",
"module": "artiq.coredevice.ad9912",
"class": "AD9912",
"arguments": {
"pll_n": 10,
"chip_select": 5,
"cpld_device": "urukul_cpld",
"sw_device": "ttl_urukul_sw1"
}
},
"urukul_ch2a": {
"type": "local",
"module": "artiq.coredevice.ad9912",
"class": "AD9912",
"arguments": {
"pll_n": 10,
"chip_select": 6,
"cpld_device": "urukul_cpld",
"sw_device": "ttl_urukul_sw2"
}
},
"urukul_ch3a": {
"type": "local",
"module": "artiq.coredevice.ad9912",
"class": "AD9912",
"arguments": {
"pll_n": 10,
"chip_select": 7,
"cpld_device": "urukul_cpld",
"sw_device": "ttl_urukul_sw3"
}
},
"urukul_ch0b": {
"type": "local",
"module": "artiq.coredevice.ad9910",
"class": "AD9910",
"arguments": {
"pll_n": 40,
"chip_select": 4,
"cpld_device": "urukul_cpld",
"sw_device": "ttl_urukul_sw0"
}
},
"urukul_ch1b": {
"type": "local",
"module": "artiq.coredevice.ad9910",
"class": "AD9910",
"arguments": {
"pll_n": 40,
"chip_select": 5,
"cpld_device": "urukul_cpld",
"sw_device": "ttl_urukul_sw1"
}
},
"urukul_ch2b": {
"type": "local",
"module": "artiq.coredevice.ad9910",
"class": "AD9910",
"arguments": {
"pll_n": 40,
"chip_select": 6,
"cpld_device": "urukul_cpld",
"sw_device": "ttl_urukul_sw2"
}
},
"urukul_ch3b": {
"type": "local",
"module": "artiq.coredevice.ad9910",
"class": "AD9910",
"arguments": {
"pll_n": 40,
"chip_select": 7,
"cpld_device": "urukul_cpld",
"sw_device": "ttl_urukul_sw3"
}
},
# AD9914 DDS
"ad9914dds0": {
"type": "local",
"module": "artiq.coredevice.ad9914",
"class": "AD9914",
"arguments": {"sysclk": 3e9, "bus_channel": 39, "channel": 0},
"arguments": {"sysclk": 3e9, "bus_channel": 27, "channel": 0},
"comment": "Comments work in DDS panel as well"
},
"ad9914dds1": {
"type": "local",
"module": "artiq.coredevice.ad9914",
"class": "AD9914",
"arguments": {"sysclk": 3e9, "bus_channel": 39, "channel": 1}
"arguments": {"sysclk": 3e9, "bus_channel": 27, "channel": 1}
},
"ad9914dds2": {
"type": "local",
"module": "artiq.coredevice.ad9914",
"class": "AD9914",
"arguments": {"sysclk": 3e9, "bus_channel": 39, "channel": 2}
"arguments": {"sysclk": 3e9, "bus_channel": 27, "channel": 2}
},
# Aliases

24
artiq/gui/logo_ver.svg
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@ -18,11 +18,11 @@
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2
conda/artiq-dev/meta.yaml
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@ -15,7 +15,7 @@ requirements:
- python >=3.5.3,<3.6
- setuptools 33.1.1
- migen 0.8 py35_0+git2d62c0c
- misoc 0.11 py35_33+git128750aa
- misoc 0.12 py35_0+git714ea689
- jesd204b 0.10
- microscope
- binutils-or1k-linux >=2.27