typo

2018-12-02 18:26:54 +08:00 · 2018-12-02 18:26:54 +08:00 · dd03fdfd1a
parent 8940009e1a
commit dd03fdfd1a
1 changed files with 1 additions and 1 deletions
--- a/artiq/compiler/transforms/llvm_ir_generator.py
+++ b/artiq/compiler/transforms/llvm_ir_generator.py
@ -151,7 +151,7 @@ class LLVMIRGenerator:
        ])

        assert self.lldatalayout in "eE"
-        self.little_endian = self.self.lldatalayout[0] == "e"
+        self.little_endian = self.lldatalayout[0] == "e"

    def needs_sret(self, lltyp, may_be_large=True):
        if isinstance(lltyp, ll.VoidType):