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Sebastien Bourdeauducq 2018-12-02 18:26:54 +08:00
parent 8940009e1a
commit dd03fdfd1a
1 changed files with 1 additions and 1 deletions
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artiq/compiler/transforms/llvm_ir_generator.py
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@ -151,7 +151,7 @@ class LLVMIRGenerator:
])
assert self.lldatalayout in "eE"
self.little_endian = self.self.lldatalayout[0] == "e"
self.little_endian = self.lldatalayout[0] == "e"
def needs_sret(self, lltyp, may_be_large=True):
if isinstance(lltyp, ll.VoidType):