Sebastien Bourdeauducq
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d26d80410e
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runtime: refactor network settings
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2019-10-19 17:56:35 +08:00 |
Sebastien Bourdeauducq
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6d5dcb4211
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runtime: enable IPv6. Closes #349
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2019-10-19 17:20:33 +08:00 |
Sebastien Bourdeauducq
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05e8f24c24
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sayma2: JESD204 synchronization
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2019-10-18 23:28:47 +08:00 |
Sebastien Bourdeauducq
|
62b49882b9
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examples/kc705: fix dds_test
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2019-10-17 07:37:00 +08:00 |
Sebastien Bourdeauducq
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a8f85860c4
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coreanalyzer: AD9914 fixes (#1376)
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2019-10-17 07:29:33 +08:00 |
Sebastien Bourdeauducq
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d42ff81144
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examples/sayma_master: update device_db
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2019-10-16 18:49:25 +08:00 |
Sebastien Bourdeauducq
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8fa3c6460e
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sayma_amc: set direction of external TTL buffer according to RTIO PHY OE
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2019-10-16 18:48:50 +08:00 |
Sebastien Bourdeauducq
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37d0a5dc19
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rtio/ttl: expose OE
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2019-10-16 18:48:20 +08:00 |
Sebastien Bourdeauducq
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bc060b7f01
|
style
|
2019-10-16 18:18:11 +08:00 |
Sebastien Bourdeauducq
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40d64fc782
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sayma: remove standalone examples (no longer supported)
|
2019-10-16 17:54:39 +08:00 |
Sebastien Bourdeauducq
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21a1c6de3f
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sayma: use SFP0 for DRTIO master
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2019-10-16 17:53:40 +08:00 |
Sebastien Bourdeauducq
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6cf06fba7b
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examples: use default IP addresses for boards
|
2019-10-16 16:18:30 +08:00 |
Tim Ballance
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c64c8b4ddc
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manual: RTIO sequence error notes (#1311)
|
2019-10-12 10:04:37 +08:00 |
David Nadlinger
|
371388ecbe
|
doc: Re-fix ARTIQ type hint formatting (#714)
This adapts the previous monkey patch for the changed location of the
attribute rendering code in Sphinx 2.0.
|
2019-10-11 17:44:38 +01:00 |
Sebastien Bourdeauducq
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9c5ff4fc04
|
manual: Nix bug 2709 fixed in Nix 2.3
|
2019-10-10 11:29:48 +08:00 |
Sebastien Bourdeauducq
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3aade3b59a
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manual: now building for nixpkgs 19.09
|
2019-10-10 10:55:44 +08:00 |
Sebastien Bourdeauducq
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314d9b5d06
|
kasli: default to 125MHz frequency for DRTIO
This is the consistent and most common option. Sayma will also eventually move to it.
|
2019-10-08 12:59:52 +08:00 |
Sebastien Bourdeauducq
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4df2c5d1fb
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sayma: prepare for SYSREF align
We will try DDMTD on the AMC first, as this is simpler and perhaps will work on v2 after the power supply fixes.
|
2019-10-08 12:30:47 +08:00 |
Sebastien Bourdeauducq
|
5ee81dc643
|
satman: define constants for JdacBasicRequest reqnos
|
2019-10-08 10:27:04 +08:00 |
Sebastien Bourdeauducq
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4b3baf4825
|
firmware: run PRBS and STPL JESD204 tests
|
2019-10-08 00:10:36 +08:00 |
Sebastien Bourdeauducq
|
03007b896e
|
sayma_amc: sma -> mcx
|
2019-10-07 20:31:35 +08:00 |
Sebastien Bourdeauducq
|
ebd5d890f1
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satman: check for JESD ready
|
2019-10-06 23:10:57 +08:00 |
Sebastien Bourdeauducq
|
90e3b83e80
|
hmc7043: turn on AMC_FPGA_SYSREF1
Florent's JESD core won't work at all without.
|
2019-10-06 22:49:00 +08:00 |
Sebastien Bourdeauducq
|
97a0dee3e8
|
jesd204: remove ibuf_disable
We use the MOSFET to mute the HMC7043 noise on hardware v2 instead.
|
2019-10-06 22:26:31 +08:00 |
Sebastien Bourdeauducq
|
1bc7743e03
|
sayma: fix hmc7043 output settings for v2 hardware
|
2019-10-06 21:50:29 +08:00 |
Sebastien Bourdeauducq
|
a421820a32
|
sayma: initialize DACs over DRTIO
|
2019-10-06 21:42:45 +08:00 |
Sebastien Bourdeauducq
|
f8e4cc37d0
|
sayma_rtm: reset and detect DACs
|
2019-10-06 20:15:27 +08:00 |
Sebastien Bourdeauducq
|
f62dc7e1d4
|
sayma: refactor JESD DAC channel groups
|
2019-10-06 20:15:09 +08:00 |
Sebastien Bourdeauducq
|
c4c884b8ce
|
ad9154: simplify, focus on AD9154 config and do not include JESD
|
2019-10-06 20:07:02 +08:00 |
Sebastien Bourdeauducq
|
fdba0bfbbc
|
satman: move now-unrelated hmc830_7043 init away from DRTIO transceiver init
|
2019-10-06 19:22:46 +08:00 |
Sebastien Bourdeauducq
|
1c6c22fde9
|
sayma_amc: HMC830_REF moved to RTM side
|
2019-10-06 18:15:37 +08:00 |
Sebastien Bourdeauducq
|
ad63908aff
|
hmc830_7043: enable_fpga_ibuf -> unmute
|
2019-10-06 18:13:59 +08:00 |
Sebastien Bourdeauducq
|
5ad65b9d30
|
hmc830_7043: remove clock_mux
|
2019-10-06 18:13:27 +08:00 |
Sebastien Bourdeauducq
|
e6ff44301b
|
sayma_amc: cleanup (v2.0 only)
|
2019-10-06 18:11:43 +08:00 |
Sebastien Bourdeauducq
|
e9b81f6e33
|
remove serwb
DRTIO is a better solution
|
2019-10-06 18:10:23 +08:00 |
Sebastien Bourdeauducq
|
7cd02d30b7
|
sayma_rtm_drtio: replace sayma_rtm
|
2019-10-06 17:59:53 +08:00 |
Sebastien Bourdeauducq
|
b3b85135a3
|
sayma_rtm_drtio: add DDMTD core, move specific cores out of SatelliteBase
|
2019-10-06 17:59:11 +08:00 |
Sebastien Bourdeauducq
|
346c985347
|
sayma_rtm_drtio: use artiq_sayma folder
|
2019-10-06 17:30:08 +08:00 |
Sebastien Bourdeauducq
|
e2a924449d
|
artiq_flash: use DRTIO RTM gateware
|
2019-10-06 17:28:14 +08:00 |
Sebastien Bourdeauducq
|
4198033657
|
sayma_rtm_drtio: cleanup (v2.0 only)
|
2019-10-06 16:42:34 +08:00 |
Sebastien Bourdeauducq
|
5612b31860
|
sayma_rtm_drtio: add HMC clock chip and DAC control
|
2019-10-06 16:15:24 +08:00 |
Sebastien Bourdeauducq
|
a8cf4c2b18
|
sayma_rtm: hwrev v2.0 by default
|
2019-10-06 13:25:30 +08:00 |
Sebastien Bourdeauducq
|
1bc5d44a7c
|
artiq_flash: do not flash RTM gateware on Sayma variants that don't need it
|
2019-10-06 13:15:50 +08:00 |
Sebastien Bourdeauducq
|
bb5ff46f7d
|
Merge branch 'wrpll'
|
2019-10-05 10:24:11 +08:00 |
Sebastien Bourdeauducq
|
7b95814cf5
|
sayma_amc: refactor, add SimpleSatellite variant
|
2019-10-05 10:24:06 +08:00 |
Sebastien Bourdeauducq
|
58b7bdcecc
|
sayma_amc: refactor RTM FPGA code
|
2019-10-05 10:24:06 +08:00 |
Sebastien Bourdeauducq
|
96fc4a21e8
|
sayma_amc: remove dummy FPGA pin assignment testing code
|
2019-10-05 10:24:06 +08:00 |
Tim Ballance
|
ada3b39f4e
|
Fix ad9910 ram mode asf scale error in polar mode
|
2019-10-04 20:14:41 +02:00 |
Tim Ballance
|
448080e71d
|
Fix ad9910 ram mode asf scale error
RAM mode amplitude to ASF conversion should be << 18 rather than << 16
|
2019-10-04 20:14:41 +02:00 |
Sebastien Bourdeauducq
|
6aa68e1715
|
sayma_rtm2: select filtered clock from Si5324
|
2019-10-04 22:56:16 +08:00 |