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Commit Graph

3649 Commits

Author SHA1 Message Date
94e68dbae4 drtio: test_full_stack (WIP) 2016-10-24 23:36:33 +08:00
a4e85081aa drtio: more simple fixes 2016-10-24 23:32:49 +08:00
029e0d95b7 drtio: simple fixes 2016-10-24 23:10:15 +08:00
c39987b617 drtio: handle underflow/sequence error CSRs 2016-10-24 20:46:55 +08:00
7dd6eb2f5e drtio: add RT write controller 2016-10-24 19:50:13 +08:00
83bec06226 drtio: fifo level -> fifo space 2016-10-24 15:59:12 +08:00
aa8e211735 drtio/rt_packets: fix 2016-10-22 13:03:35 +08:00
449d1c4dc6 rtio: export CDC modules 2016-10-22 13:03:10 +08:00
67c19ab178 drtio: RTPacketMaster RX, untested 2016-10-22 01:04:14 +08:00
3b4a40401a drtio: RTPacketMaster TX (WIP) 2016-10-21 22:46:14 +08:00
1e313afe64 drtio: CrossDomainNotification 2016-10-21 22:45:45 +08:00
c71c4c89e0 drtio: change data direction in _CrossDomainRequest 2016-10-21 22:44:47 +08:00
6a88229e6a drtio: CrossDomainRequest 2016-10-20 23:37:59 +08:00
9790c5d9ed drtio/iot: FIFO level 2016-10-19 18:04:03 +08:00
71480c4d15 drtio: fix mmcm_mult 2016-10-18 17:28:03 +08:00
e7dbed3b02 gateware: KC705 satellite target 2016-10-17 19:23:45 +08:00
9752ffe3d1 drtio: various fixes 2016-10-17 19:23:08 +08:00
cce29e8b83 gateware/spi: fix import 2016-10-17 14:47:19 +08:00
d3b274fc4d drtio: synchronizer MMCM 2016-10-16 17:40:58 +08:00
03d3a85e75 drtio: RX clock alignment and ready 2016-10-15 18:36:27 +08:00
08e4aa3e3f drtio: GTX WIP 2016-10-14 00:36:13 +08:00
c548a65ec3 drtio: clock domains 2016-10-14 00:34:59 +08:00
018f6d1b52 drtio: implement basic IOT 2016-10-11 17:59:22 +08:00
a40b39e9a2 drtio: structure 2016-10-10 23:12:12 +08:00
87ec333f55 drtio: implement basic writes, errors, fifo levels on satellite 2016-10-10 00:13:41 +08:00
23b3302200 drtio: implement TSC load in satellite 2016-10-07 19:30:53 +08:00
43caffc168 drtio: self-checking echo test 2016-10-07 17:31:51 +08:00
0574e882d2 drtio: basic RT packet echo test 2016-10-07 15:36:32 +08:00
cb0d1549c6 drtio: add rt_packets TX datapath, fixes 2016-10-07 15:35:29 +08:00
76bac21d14 drtio: RT RX datapath, untested 2016-10-06 18:51:20 +08:00
1e0c6d6d5d drtio: monitor received link_init 2016-09-30 11:25:06 +08:00
cefb9e1405 drtio: add full link layer 2016-09-27 21:41:57 +08:00
08772f7a71 drtio: add RX ready signaling 2016-09-27 19:02:54 +08:00
95d7cba34a drtio: fixes, add aux packet test 2016-09-27 12:46:01 +08:00
e59142e344 drtio: use additive scrambler reset by link init 2016-09-27 11:38:05 +08:00
8a92c2c7e5 drtio: add RX link layer, fixes, simple loopback demo 2016-09-27 11:23:29 +08:00
4e47decdbc drtio: add scrambler/descrambler and test 2016-09-26 14:14:14 +08:00
fa83ad0d9c drtio: add TX link layer 2016-09-26 12:53:10 +08:00
2701b914e2 conda: update migen version requirements 2016-09-24 21:02:19 +08:00
8280e72e90 gateware: use new misoc CSR mapping API 2016-09-24 20:48:37 +08:00
whitequark
956f64906d Rust: fix incorrect use of lwip API. 2016-09-23 05:20:15 +00:00
whitequark
ce05eee80c Rust: style fix. 2016-09-23 05:20:04 +00:00
fac0c68cd1 novatech409b: fix get_status 2016-09-23 11:03:50 +08:00
2d6171e8c4 dashboard: make state restore failure on experiment opening non-fatal 2016-09-21 19:23:06 +08:00
2bb90a4449 pipistrello: shrink a few more fifos 2016-09-21 02:29:05 +02:00
whitequark
9a24a81f14 Rust: update network stack to provide blocking impls. 2016-09-20 14:03:31 +00:00
whitequark
dec394bc13 Rust: port std::error into libstd_artiq.
See https://github.com/jethrogb/rust-core_io/issues/3.
2016-09-20 14:02:53 +00:00
whitequark
1c7e1dd645 Rust: import core_io crate into libstd_artiq.
Unfortunately the crate does not work out of the box with custom
Rust builds, and forking it makes little sense over just embedding
it here. See https://github.com/jethrogb/rust-core_io/issues/2.
2016-09-20 08:28:00 +00:00
52f935dcfb README: GPLv3+ 2016-09-15 09:51:33 -04:00
e4d1d0a309 RELEASE_NOTES: 2.0rc2 2016-09-14 21:54:32 -04:00