668450db26
sayma_amc: add serwb
2017-08-21 18:11:29 -04:00
0459a70cf6
sayma_amc: cleanup, fix RTM UART forwarding
2017-08-21 16:49:42 -04:00
1f2b373d09
sayma_rtm: remove unnecessary serwb_control
2017-08-21 16:37:13 -04:00
bfea297279
targets: add Sayma RTM
2017-08-21 15:58:01 -04:00
53c7f92fdc
serwb: add __init__.py and expose submodules
2017-08-21 15:57:43 -04:00
dac3a78b75
serwb: style, use migen, fix imports
2017-08-21 12:35:59 -04:00
Florent Kermarrec
da90a0fa12
Add test for Etherbone
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Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ec62242659910ad1726beb00ff15b3f0a406615
2017-08-21 12:31:49 -04:00
Florent Kermarrec
44dc76e42e
Add serial Wishbone bridge
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Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ce2cba87896d056819dc2edc54f0453a86162c3
2017-08-21 12:22:05 -04:00
d6b624dfbe
sayma_amc: connect RTM serial and second serial
2017-08-20 19:01:55 -04:00
bee4902323
add Sayma AMC standalone target
2017-08-20 11:47:45 -04:00
1dab7df846
kc705_sma_spi: fix permissions
2017-08-20 10:54:24 -04:00
df4f38a1e4
kc705: add pullup on SD card MISO
2017-07-24 22:26:16 +08:00
a201a9abd9
drtio: multilink transceiver interface
2017-07-18 13:27:33 +08:00
9045b4cc19
drtio: initial firmware support for multi-link
2017-07-18 00:40:21 +08:00
4deb5f6a45
gateware: use new MiSoC Wishbone address system
2017-07-13 19:16:49 +08:00
mntng
40ca951750
kc705: add SPI bus for memory card
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This will be useful for SPI unit tests using a SD card as victim.
2017-07-12 00:27:44 +08:00
7b130a2c32
sawg: confirm smooth(order=3)
2017-07-07 11:36:03 +02:00
2f1029c292
Revert "sawg: advance dds 1/2 by one sample group"
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This reverts commit 8e0a1cbdc8#772
The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.
2017-07-04 17:55:19 +02:00
8e0a1cbdc8
sawg: advance dds 1/2 by one sample group
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closes #772
2017-07-04 16:51:58 +02:00
91ca9fbcad
sawg: also give offset some headroom
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closes #771
2017-07-04 16:50:06 +02:00
78d1f0fdf6
sawg: fix PhasedAccu resets
2017-07-04 11:56:21 +02:00
Florent Kermarrec
2910b1be5e
artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect
2017-07-04 10:48:06 +02:00
838127d914
rtio: break DMA timing path
2017-07-02 10:24:01 +08:00
911ee4a959
rtio: make pipelined logic reset_less
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* latency-corrected counters
* registered error logic
2017-06-29 12:55:32 +02:00
600a48ac61
dsp.fir: cleanup
2017-06-29 12:18:48 +02:00
dca662a743
dsp.fir: pipeline final systolic adder
2017-06-29 11:33:19 +02:00
32a33500c8
dsp.fir: actively cull zero delays
2017-06-29 11:24:56 +02:00
f520d4a768
rtio: undo _RelaxedAsyncResetSynchronizer
2017-06-28 22:08:15 +02:00
3cbbcdfe96
sawg: don't enable_replace for Config
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closes #762
2017-06-28 20:31:40 +02:00
f2632e0fd1
sawg: adapt latency to fir changes
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closes #748
2017-06-28 20:12:30 +02:00
e7db2c6578
dsp.accu: reset_less outputs
2017-06-28 20:04:58 +02:00
6bb994228f
dsp.fir: drop x shift
2017-06-28 19:55:15 +02:00
01847271c5
rtio: use reset_less signal for reset fanout
2017-06-28 19:43:55 +02:00
b9859cc0c3
dsp.fir: remove old/wrong comment
2017-06-28 19:21:57 +02:00
55b5b87490
fir: simplify latency compensation
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Don't try to tweak out the last bit of latency by feeding the HBF input
early. Instead feed it late so the interpolated samples are early and
the latency is an even multiple of the super-sample cycle.
2017-06-28 19:13:43 +02:00
d1e5dd334f
sawg: use pipeline reset
2017-06-28 19:09:39 +02:00
6418205906
dsp.fir: use pipelin-reset
2017-06-28 19:09:21 +02:00
07f5e99140
dsp/sat_add: works after previous changes
2017-06-22 18:24:22 +02:00
f78d5a87e9
dsp/test: skip and fix sat_add
2017-06-22 18:01:31 +02:00
47928a2c0d
sawg: disable limiter
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temporary workaround to permit testing other aspects
2017-06-22 17:31:04 +02:00
cd2ac53bc5
dsp/sat_add: make width mandatory
2017-06-22 17:28:39 +02:00
9b940aa876
dsp/sat_add: spell out logic more
2017-06-22 16:55:13 +02:00
d0cf0f2b87
sawg/limiter: make signed signals explicitly
2017-06-22 13:44:36 +02:00
694f8d784c
dsp/tools: unittest sat_add
2017-06-22 11:29:56 +02:00
bd1438d28e
sawg: wrap limits init values
2017-06-22 10:26:29 +02:00
cccd01e81e
sawg: cleanup sat_add logic
2017-06-22 10:26:29 +02:00
5f6e665158
test/sawg: patch delay_mu
2017-06-22 10:26:29 +02:00
570f2cc1ff
dsp/tools/SatAdd: fix reuse of clipped signal
2017-06-22 10:26:29 +02:00
4b3aad2563
sawg: clean up Config
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* unify I and Q data limiters. there is no conceivable way why they
would be different.
* reorder clr bits to be like consistent
* move the sat add limiter to before the hbf again
2017-06-22 10:26:29 +02:00
f4c6879c76
sawg: special case Config RTIO address
2017-06-22 10:26:29 +02:00
