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5d5853d3f8
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examples/helloworld: use new nmigen read_port comb API
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2019-07-03 11:29:07 +08:00 |
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1c0c4cee1b
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nmigen: bump
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2019-07-03 11:27:46 +08:00 |
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68e1b1e778
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nmigen-boards: bump
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2019-07-03 09:05:33 +08:00 |
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2f200bbf8a
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nmigen: bump
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2019-07-03 09:00:24 +08:00 |
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29548b4a33
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nmigen: fix hash
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2019-06-29 13:27:55 +08:00 |
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466eed2df9
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README: add nMigen link
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2019-06-24 18:26:44 +08:00 |
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87b4b357c3
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README: add some details
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2019-06-24 18:25:44 +08:00 |
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8d327d4f6f
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nmigen: bump
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2019-06-13 13:46:18 +08:00 |
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4af5e6fb9e
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add experimental LiteDRAM package
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2019-06-13 09:36:12 +08:00 |
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4c7ca4a8d1
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add experimental LiteX package
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2019-06-12 17:22:54 +08:00 |
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92671d534c
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nmigen-boards: add
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2019-06-11 22:53:03 +08:00 |
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6d837f4662
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nmigen: bump
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2019-06-11 22:52:43 +08:00 |
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6d2449b973
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nmigen: fix URL
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2019-06-11 22:47:38 +08:00 |
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b93ee35a7d
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update README
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2019-06-10 15:01:58 +08:00 |
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0bb4a0da46
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more markdown fixing
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2019-06-10 14:51:34 +08:00 |
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630048ae5f
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gitea doesn't like rst
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2019-06-10 14:51:07 +08:00 |
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40f869632b
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document how to build helloworld soc
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2019-06-10 14:49:55 +08:00 |
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3598e08212
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symbiflow: 100MHz timing (HACK)
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2019-06-09 00:06:17 +08:00 |
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d9b42a0807
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clean up firmware compilation
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2019-06-09 00:05:40 +08:00 |
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fd05fa560f
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firmware: compile for riscv32i
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2019-06-08 23:01:37 +08:00 |
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328a521632
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simplesoc_ecp5: run simulation longer
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2019-06-08 23:00:57 +08:00 |
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c7bda2b144
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compile Rust core crate for riscv32i
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2019-06-08 21:52:33 +08:00 |
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03dc4f6e32
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add RISCV GCC
Needed to refresh riscv and riscv-rt Rust crates.
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2019-06-08 21:50:47 +08:00 |
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033659344f
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Revert "Revert "reinstate riscv32i""
Custom rustc targets with JSON come with a messed up TARGET environment variable and lots of things break.
This reverts commit b22d85ba52.
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2019-06-08 19:31:41 +08:00 |
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8388018db7
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also build riscv64 binutils
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2019-06-08 19:25:38 +08:00 |
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b22d85ba52
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Revert "reinstate riscv32i"
This reverts commit 06d825f63d.
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2019-06-08 18:48:50 +08:00 |
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06d825f63d
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reinstate riscv32i
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2019-06-08 17:35:27 +08:00 |
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75e9310097
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simplesoc_ecp5: add simulation
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2019-06-08 17:30:49 +08:00 |
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83ffe66f70
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simplesoc_ecp5: add blinking LED
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2019-06-07 23:17:19 +08:00 |
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2cfafcdf20
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firmware: match simplesoc memory addresses
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2019-06-07 23:17:03 +08:00 |
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ad4f00e93d
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simplesoc_ecp5: load firmware
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2019-06-06 18:11:54 +08:00 |
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a53c470d17
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nmigen: bump
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2019-06-06 18:11:31 +08:00 |
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713f644072
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minerva: bump
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2019-06-06 18:04:56 +08:00 |
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a203307108
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reorganize
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2019-06-06 17:25:11 +08:00 |
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63664ab959
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build .bin firmware image
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2019-06-06 17:17:45 +08:00 |
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d2391e0aa1
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build firmware with Nix
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2019-06-06 13:19:17 +08:00 |
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b6c53406ea
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show LLVM in hydra
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2019-06-06 12:24:48 +08:00 |
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3edb51a646
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fix syntax issue
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2019-06-06 12:12:40 +08:00 |
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85f7b2bf15
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use overlay instead of passing llvm/rustc/cargo around
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2019-06-06 12:05:48 +08:00 |
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78f67f82d3
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firmware: simulable demo
Run:
qemu-system-riscv32 -nographic -machine sifive_u -kernel target/riscv32imc-unknown-none-elf/release/helloworld
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2019-06-06 10:33:29 +08:00 |
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b5ac2e7303
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add simple Rust firmware (WIP)
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2019-06-06 00:12:17 +08:00 |
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f707295646
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use the GNU linker
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2019-06-06 00:07:53 +08:00 |
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cf86c11dce
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binutils: use unknown-elf
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2019-06-06 00:06:29 +08:00 |
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aa1c3726f3
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attempt to use lld linker
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2019-06-05 23:46:29 +08:00 |
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d5c288c20b
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rustc: disable lld
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2019-06-05 23:42:39 +08:00 |
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1361c6ae9e
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Revert "llvm: only build x86 and riscv"
This reverts commit b17ec6fb1f.
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2019-06-05 23:41:22 +08:00 |
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b17ec6fb1f
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llvm: only build x86 and riscv
Attempting to fix llvm-lld breakage on msp430 by disabling msp430.
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2019-06-05 23:19:51 +08:00 |
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52cc7722a0
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add nix-shell file for firmware compilation
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2019-06-05 23:08:55 +08:00 |
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6ad1d993c6
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rustc: remove riscv32i support
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2019-06-05 23:07:49 +08:00 |
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f929be260a
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build cargo
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2019-06-05 23:06:57 +08:00 |
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