Next-generation FPGA SoC toolkit

Sebastien Bourdeauducq 033659344f Revert "Revert "reinstate riscv32i"" ... Custom rustc targets with JSON come with a messed up TARGET environment variable and lots of things break. This reverts commit b22d85ba52.		2019-06-08 19:31:41 +08:00
compilers	Revert "Revert "reinstate riscv32i""	2019-06-08 19:31:41 +08:00
cores	minerva: bump	2019-06-06 18:04:56 +08:00
eda	nmigen: bump	2019-06-06 18:11:31 +08:00
examples	simplesoc_ecp5: add simulation	2019-06-08 17:30:49 +08:00
firmware	also build riscv64 binutils	2019-06-08 19:25:38 +08:00
heavycomps	add wishbone components	2019-05-02 12:53:08 +08:00
.gitignore	add nix-build results to .gitignore	2019-03-25 23:36:52 +08:00
default.nix	also build riscv64 binutils	2019-06-08 19:25:38 +08:00
heavycomps.nix	add component library with UART	2019-03-19 16:52:02 +08:00
overlay.nix	Revert "Revert "reinstate riscv32i""	2019-06-08 19:31:41 +08:00
release.nix	reorganize	2019-06-06 17:25:11 +08:00