Next-generation FPGA SoC toolkit
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Sebastien Bourdeauducq 4af5e6fb9e add experimental LiteDRAM package 2 years ago
compilers compile Rust core crate for riscv32i 2 years ago
cores add experimental LiteDRAM package 2 years ago
eda nmigen-boards: add 2 years ago
examples simplesoc_ecp5: run simulation longer 2 years ago
firmware gitea doesn't like rst 2 years ago
heavycomps add wishbone components 3 years ago
.gitignore add nix-build results to .gitignore 3 years ago update README 2 years ago
default.nix add experimental LiteDRAM package 2 years ago
heavycomps.nix add component library with UART 3 years ago
overlay.nix clean up firmware compilation 2 years ago
release.nix reorganize 2 years ago


A FPGA SoC framework embracing cutting-edge open source technologies (nMigen, Yosys, SymbiFlow, Minerva, Nix, Rust).

This is work in progress!

"Hello World" SoC demo

Softcore RISC-V system-on-chip on the Lattice ECP5 Versa board, built with a 100% Verilog/VHDL-free and 100% open source toolchain. Runs a Rust "hello world" program.

Use nixpkgs unstable (known to work with ae71c13). Check for the status of the build with other nixpkgs versions.

Optional: set up the M-Labs key and binary substituter for Nix (otherwise Nix will recompile LLVM, rustc, etc. on your machine). Create the file ~/.config/nix/nix.conf with the following contents:

substituters =
trusted-public-keys =

Run nix-build -A simplesoc_ecp5 release.nix

Bypass the ispCLOCK device using the jumpers on your board.

Create a versa.cfg file with:

interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0xfff8 0xfffb
reset_config none
adapter_khz 5000
jtag newtap ecp5 tap -irlen 8 -expected-id 0x01112043

Load the bitstream openocd -f versa.cfg -c "transport select jtag; init; svf result/top.svf; exit".

Watch the UART output at 115200bps.

Questions, comments: or IRC #m-labs on Freenode.