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Next-generation FPGA SoC toolkit
101 Commits 2 Branches 0 Tags 412 KiB
Nix 60.4%
Python 29.9%
Diff 7.1%
Rust 2.4%
RPC 0.2%
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Sebastien Bourdeauducq 3598e08212 symbiflow: 100MHz timing (HACK) 2019-06-09 00:06:17 +08:00
compilers compile Rust core crate for riscv32i 2019-06-08 21:52:33 +08:00
cores minerva: bump 2019-06-06 18:04:56 +08:00
eda symbiflow: 100MHz timing (HACK) 2019-06-09 00:06:17 +08:00
examples simplesoc_ecp5: run simulation longer 2019-06-08 23:00:57 +08:00
firmware clean up firmware compilation 2019-06-09 00:05:40 +08:00
heavycomps add wishbone components 2019-05-02 12:53:08 +08:00
.gitignore add nix-build results to .gitignore 2019-03-25 23:36:52 +08:00
default.nix compile Rust core crate for riscv32i 2019-06-08 21:52:33 +08:00
heavycomps.nix add component library with UART 2019-03-19 16:52:02 +08:00
overlay.nix clean up firmware compilation 2019-06-09 00:05:40 +08:00
release.nix reorganize 2019-06-06 17:25:11 +08:00