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compilers
|
compile Rust core crate for riscv32i
|
2019-06-08 21:52:33 +08:00 |
|
cores
|
minerva: bump
|
2019-06-06 18:04:56 +08:00 |
|
eda
|
symbiflow: 100MHz timing (HACK)
|
2019-06-09 00:06:17 +08:00 |
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examples
|
simplesoc_ecp5: run simulation longer
|
2019-06-08 23:00:57 +08:00 |
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firmware
|
clean up firmware compilation
|
2019-06-09 00:05:40 +08:00 |
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heavycomps
|
add wishbone components
|
2019-05-02 12:53:08 +08:00 |
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.gitignore
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add nix-build results to .gitignore
|
2019-03-25 23:36:52 +08:00 |
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default.nix
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compile Rust core crate for riscv32i
|
2019-06-08 21:52:33 +08:00 |
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heavycomps.nix
|
add component library with UART
|
2019-03-19 16:52:02 +08:00 |
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overlay.nix
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clean up firmware compilation
|
2019-06-09 00:05:40 +08:00 |
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release.nix
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reorganize
|
2019-06-06 17:25:11 +08:00 |
