Commit Graph

7993 Commits

Author SHA1 Message Date
e803830b3b fastino: support wide RTIO interface and channel groups 2020-03-05 17:55:04 +00:00
8dbf30b23e manual: mention integrated Kasli JTAG 2020-03-02 18:42:01 +08:00
8451e58fbe ad9912: fix ftw width docstring 2020-02-27 02:11:12 +08:00
Paweł K
2a909839ff
artiq_flash: added option of specifying another username when connecting through SSH. (#1429)
Signed-off-by: Paweł Kulik <pawel.kulik@creotech.pl>
2020-02-19 19:44:11 +08:00
6d26def3ce sayma: drive filtered_clk_sel on master variant 2020-02-06 22:28:49 +08:00
52ec849008 sayma: fix sysref_delay_dac 2020-02-05 19:04:01 +08:00
c7de1f2e6b metlino: drive clock muxes 2020-02-05 00:06:34 +08:00
bf9f4e380a si5324: program I2C mux on Metlino 2020-02-03 18:07:59 +08:00
ffb24e9fff artiq_flash: use correct proxy bitstream for Metlino 2020-02-03 18:07:26 +08:00
5f8e20b1a1 artiq_sinara_tester: fix device_db filename 2020-01-31 10:26:58 +08:00
dfa033eb87 wrpll: new collector from Weida/Tom 2020-01-24 10:31:52 +08:00
dee16edb78 wrpll: DDMTD sampler double latching 2020-01-22 19:16:26 +08:00
f4d8f77268 turn kasli_tester into a frontend tool 2020-01-21 16:13:04 +08:00
bfcbffcd8d update smoltcp
This disables the 'log' features which does not compile, and may break net_trace. To be investigated later.
2020-01-21 13:58:23 +08:00
82cdb7f933 typo 2020-01-21 10:07:13 +08:00
248230a89e fastino: style 2020-01-20 13:25:00 +01:00
c45a872cba fastino: fix init, set_cfg 2020-01-20 13:25:00 +01:00
2c4e5bfee4 fastino: add [WIP] 2020-01-20 13:25:00 +01:00
8f9948a1ff kasli_sawgmaster: add basemod programming example 2020-01-20 20:14:24 +08:00
e427aaaa66 basemod_att: fix imports 2020-01-20 20:14:24 +08:00
62a52cb086 sayma: do not pollute the log with DAC status on success 2020-01-20 20:14:24 +08:00
6b428ef3be sayma: initialize DAC before testing jesd::ready 2020-01-20 20:14:24 +08:00
7ab0282234 adf5355: style 2020-01-20 13:13:08 +01:00
9368c26d1c mirny: add to manual 2020-01-20 13:13:08 +01:00
Etienne Wodey
da531404e8 artiq_ddb_template: add Mirny support
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2020-01-20 13:13:08 +01:00
01a6e77d89 mirny: add
* This targets unrelease CPLD gateware (https://github.com/quartiq/mirny/issues/1)
* includes initial coredevice driver, eem shims, and kasli_generic tooling
* addresses the ARTIQ side of #1130
* Register abstraction to be written

Signed-off-by: Robert Jördens <rj@quartiq.de>
2020-01-20 13:13:08 +01:00
ec03767dcf sayma: improve DAC status report 2020-01-20 18:22:06 +08:00
5c299de3b4 sayma: print DAC status on JESD not ready error 2020-01-20 18:21:29 +08:00
45efee724e sayma: add JESD204 PHY done diagnostics 2020-01-20 12:47:31 +08:00
6c3e71a83a wrpll: cleanup 2020-01-18 09:43:43 +08:00
344f8bd12a wrpll: collector patch from Weida 2020-01-18 09:42:58 +08:00
833f428391 sayma: fix hmc542 to/from mu 2020-01-16 09:10:32 +08:00
6c948c7726 sayma: RF switch control is active-low on Basemod, invert 2020-01-16 08:59:52 +08:00
50302d57c0 wrpll: more careful I2C timing 2020-01-14 20:03:46 +08:00
105dd60c78 wrpll: ADPLLProgrammer mini test bench and fixes 2020-01-14 16:52:25 +08:00
3242e9ec6c wrpll: loop test 2020-01-13 22:31:57 +08:00
8ec0f2e717 wrpll: implement ADPLLProgrammer 2020-01-13 22:30:11 +08:00
d5895b8999 wrpll: adpll -> set_adpll 2020-01-13 20:46:36 +08:00
e7ef23d30c wrpll: use CONFIG_CLOCK_FREQUENCY and rtio_frequency in trim_dcxos 2020-01-13 20:44:15 +08:00
ea3bce6fe3 wrpll: wait for settling time after setting ADPLL 2020-01-13 20:43:34 +08:00
d685619bcd wrpll: collector code modifications from Weida 2020-01-13 20:42:41 +08:00
9d7196bdb7 update copyright year 2020-01-13 19:33:44 +08:00
e87d864063 wrpll: print ADPLL offsets 2020-01-13 19:32:30 +08:00
8edbc33d0e wrpll: calculate initial ADPLL offsets 2020-01-13 19:29:10 +08:00
9dd011f4ad firmware: remove bitrotten Sayma code 2020-01-13 18:47:54 +08:00
583a18dd5f firmware: expose fmod to kernels. Closes #1417 2020-01-10 14:33:02 +08:00
David Nadlinger
d8c81d6d05 compiler: Other types microoptimisations
Interestingly enough, these actually seem to give a measurable
speedup (if small – about 1% improvement out of 6s whole-program
compile-time in one particular test case).

The previous implementation of is_mono() had also interesting
behaviour if `name` wasn't given; it would test only for the
presence of any keys specified via keyword arguments,
disregarding their values. Looking at uses across the current
ARTIQ codebase, I could neither find a case where this would
have actually been triggered, nor any rationale for it.

With the short-circuited implementation from this commit,
is_mono() now checks name/all of params against any specified
conditions.
2020-01-01 08:49:19 +00:00
David Nadlinger
2c34f0214b compiler: Short-circuit Type.unify() with identical other type
This considerably improves performance; ~15% in terms of total
artiq_run-to-kernel-compiled duration in one test case.
2020-01-01 08:49:19 +00:00
eebae01503 artiq_client: add back quiet-verbose args for submission
close #1416
regression introduced in 3fd6962
2019-12-31 13:00:26 +01:00
3f32d78c0e wrpll: simple ADPLL test 2019-12-31 12:12:29 +08:00