forked from M-Labs/artiq
wrpll: wait for settling time after setting ADPLL
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@ -267,6 +267,7 @@ mod si549 {
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write(dcxo, 231, adpll as u8)?;
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write(dcxo, 232, (adpll >> 8) as u8)?;
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write(dcxo, 233, (adpll >> 16) as u8)?;
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clock::spin_us(100);
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Ok(())
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}
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}
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