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66 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 65567e1201 soc/target: remap RTIO to avoid conflict with Ethernet MAC+PHY 2014-11-21 15:51:51 -08:00
Sebastien Bourdeauducq 346cca9e90 soc/target: remap RTIO to avoid conflict with spiflash and ddrphy in MiSoC 2014-10-21 18:40:08 +08:00
Sebastien Bourdeauducq af0cd902d3 get frequency from RTIO, support fractional frequencies 2014-09-26 17:24:06 +08:00
Sebastien Bourdeauducq f0f65ba3a7 soc/target: add optional test signal generator 2014-09-17 19:53:55 +08:00
Sebastien Bourdeauducq 2c0b6ff4cc soc/target: connect FUD to RTIO 2014-09-11 23:11:22 +08:00
Sebastien Bourdeauducq 8d7591dfcf more PEP8 2014-09-05 17:06:41 +08:00
Sebastien Bourdeauducq 4915b4b5aa PEP8 2014-09-05 12:03:22 +08:00
Sebastien Bourdeauducq 1ed808e848 soc/target: share base PPro design with MiSoC 2014-08-03 12:26:15 +08:00
Sebastien Bourdeauducq f03ae5e5b0 soc/rtio: separate PHY, add OE and fine timestamp in FIFO 2014-07-24 23:50:20 -06:00
Robert Jördens 005d66c7cd soc/dds: fix timing 2014-07-22 17:44:41 -06:00
Sebastien Bourdeauducq 2358b218bf soc: add DDS interface core 2014-07-22 11:37:53 -06:00
Sebastien Bourdeauducq 5573cf3688 soc: add tester IO 2014-07-22 10:45:59 -06:00
Sebastien Bourdeauducq ede3667fd3 soc/target: use only 8 TTL channels for now 2014-07-20 18:38:41 -06:00
Sebastien Bourdeauducq 3b4bb41a19 add basic output-only untested RTIO core 2014-07-16 19:13:11 -06:00
Sebastien Bourdeauducq d804f1199e soc: add LED 2014-07-05 22:44:20 +02:00
Sebastien Bourdeauducq 6072f0c42f Basic SoC and runtime design 2014-07-04 17:49:08 +02:00