f5a1001114
suservo: add device database and artiq_flash variant
2018-03-21 08:53:26 +00:00
1fb5907362
kasli: add SUServo variant (Sampler-Urukul Servo)
2018-03-21 08:53:26 +00:00
f74d5772f4
sampler: add wide eem definition
2018-03-21 08:53:26 +00:00
32f22f4c9c
sayma: disable SERDES TTL entirely
...
Timing closure becomes very random, even at 4X.
2018-03-21 13:03:48 +08:00
f8c2d54e75
ttl_serdes_ultrascale: configurable SERDES ratio. Also try X4 on Sayma
2018-03-21 13:01:38 +08:00
9c2d343052
sayma: use SERDES RTIO TTL
...
This is not enabled on the standalone design as it breaks timing.
2018-03-21 10:53:52 +08:00
9ad1fd8f25
urukul: add comment and doc about the AD9910 MASTER_RESET
2018-03-20 17:40:03 +01:00
f17c0abfe4
urukul: don't pulse DDS_RST on init
...
closes m-labs/artiq#940
Apparently, if the DDS are reset, every other time they don't work
properly.
2018-03-20 16:10:26 +00:00
a185e8dc52
urukul: fix MASK_NU offset
2018-03-20 16:10:11 +00:00
f4719ae24b
sdram: clean up console output
2018-03-20 15:42:49 +01:00
206664afd9
sdram: compact read_level output
2018-03-20 10:16:05 +00:00
495625b99d
bootloader: repeat memory test 4 times
2018-03-20 09:57:49 +00:00
6fb0cbfcd3
sdram: clean up, make read_level robust to wrap around
...
* fix a few rust warnings
* also do eye scans on kintex
2018-03-20 09:57:49 +00:00
3abb378fbe
i2c: unused variable
2018-03-20 09:56:26 +00:00
c8020f6bbd
ttl_serdes_generic: fix/upgrade test
2018-03-20 16:46:57 +08:00
a5825184b7
add ttl_serdes_ultrascale (untested)
2018-03-20 16:07:23 +08:00
fad066f1aa
ttl_serdes_7series: cleanup indentation
...
Inconsistent with other code and confuses text editors.
2018-03-20 15:50:04 +08:00
276b0c7f06
sdram: reject read delay wrap arounds
2018-03-20 00:28:41 +01:00
65379b1f7a
conda: bump migen, misoc
...
* xilinx ODDR2 SRTYPE
* flterm leak
* I/ODELAY VTC/reset sequencing
* sayma SDRAM clock buffer LOC
2018-03-19 19:58:52 +01:00
4b3f408143
sdram: simplify read level scan
2018-03-19 18:41:56 +00:00
845784c180
kusddrphy: use first and last tap that yield many valid reads
2018-03-19 17:54:26 +00:00
ed2e0c8b34
sayma/sdram/scan: test each tap 1024 times
2018-03-20 00:59:31 +08:00
hartytp
a27b5d88c2
Novogorny driver, remove unused imports ( #964 )
...
* Novogorny driver, remove unused imports
* more unused imports
* oops, one final one!
2018-03-19 11:58:14 +01:00
7a7ff6d2dd
Merge pull request #963 from hartytp/kasli_zotino_sampler
...
Add Zotino and Sampler functions to Kasli. Add Zotino to Kasli EEM 7 …
2018-03-19 10:52:50 +01:00
Thomas Harty
37d431039d
Fix typos.
...
Reduce ififo depth to 4 for Zotino.
2018-03-19 09:42:18 +00:00
whitequark
c86df8e13e
firmware: try to unstuck the I2C bus if it gets stuck.
...
Fixes #957 .
2018-03-19 06:23:23 +00:00
Thomas Harty
c4fa44bc62
Add Zotino and Sampler functions to Kasli. Add Zotino to Kasli EEM 7 on OptiClock.
2018-03-18 00:25:43 +00:00
f39b7b33e8
ad5360: whitespace [nfc]
2018-03-17 18:51:17 +01:00
2eadb08f8c
Merge pull request #962 from hartytp/ad5360
...
Fix AD5360 after migration to SPI2
2018-03-17 18:48:34 +01:00
ion
c1439bfd3b
Fix AD5360 after migration to SPI2
2018-03-17 11:37:11 +00:00
whitequark
c4bfc83b38
conda: mark the artiq-build output package as noarch, not toplevel.
...
This also changes `noarch: python` to `noarch: generic` since
this is semantically correct; the bitstream/firmware packages
contain no Python code.
Fixes #960 .
2018-03-15 23:17:05 +00:00
whitequark
4b5a78e231
compiler: do not pass files to external tools while they are opened.
...
This fixes access violations on Windows that are present both with
input and output files. For some reason, Cygwin-compiled binutils
did not exhibit this problem, but MSYS-compiled binutils do.
Fixes #961 .
2018-03-15 22:21:29 +00:00
whitequark
5cb2602021
artiq_devtool: flash gateware if -g is passed.
2018-03-15 08:33:53 +00:00
whitequark
9ea7d7a804
firmware: allow building without system UART.
2018-03-14 18:34:31 +00:00
whitequark
158ceb0881
artiq_devtool: add kasli target.
2018-03-14 18:13:13 +00:00
a315ecd10b
rtio/ttl_serdes_7series: reset IOSERDES ( #958 )
2018-03-14 09:01:29 +08:00
2fdc180601
dsp/fir: outputs reset_less (pipelined)
2018-03-13 17:11:50 +00:00
2edf65f57b
drtio: fix satellite minimum_coarse_timestamp clock domain ( #947 )
2018-03-13 00:20:57 +08:00
999ec40e79
bootloader: print gateware ident
2018-03-13 00:11:25 +08:00
2caeea6f25
update copyright year
2018-03-13 00:09:13 +08:00
1d081ed6c2
drtio: print diagnostic info on satellite write underflow ( #947 )
2018-03-12 23:41:19 +08:00
Florent Kermarrec
eb6e59b44c
sayma_rtm: fix serwb timing constraints (was causing the gated clock warning)
2018-03-12 11:25:29 +01:00
6dfebd54dd
ttl_serdes_7series: use correct IBUFDS_INTERMDISABLE port names
2018-03-12 10:37:33 +08:00
44277c5b7e
conda: bump migen/misoc
2018-03-11 10:11:42 +08:00
a04bd5a4fd
spi2: xfers take one more cycle until ~busy
2018-03-09 20:48:17 +01:00
Florent Kermarrec
5af4609053
libboard/sdram: limit write leveling scan to "512 - initial dqs taps delay" on ultrascale
2018-03-09 19:06:47 +01:00
Florent Kermarrec
a95cd423cc
libboard/sdram: add gap for write leveling
2018-03-09 18:53:57 +01:00
fc3d97f1f7
drtio: remove spurious multichannel transceiver clock constraints
...
They used to cause (otherwise harmless) Vivado critical warnings.
2018-03-09 22:46:27 +08:00
caf7b14b55
kasli: generate fine RTIO clock in DRTIO targets, separate RTIO channel code
2018-03-09 22:36:16 +08:00
e65e2421a3
conda: bump migen/misoc
2018-03-09 22:35:40 +08:00
