forked from M-Labs/artiq
sayma_rtm: fix serwb timing constraints (was causing the gated clock warning)
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@ -159,11 +159,7 @@ class SaymaRTM(Module):
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csr_devices.append("serwb_phy_rtm")
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serwb_phy_rtm.serdes.cd_serwb_serdes.clk.attr.add("keep")
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serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk.attr.add("keep")
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serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
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platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes.clk, 40*1e9/serwb_pll.linerate),
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platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk, 2*1e9/serwb_pll.linerate),
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platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk, 8*1e9/serwb_pll.linerate)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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serwb_phy_rtm.serdes.cd_serwb_serdes.clk,
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