dsp/fir: outputs reset_less (pipelined)

2018-03-13 17:11:50 +00:00 · 2018-03-13 17:11:50 +00:00 · 2fdc180601
commit 2fdc180601
parent 2edf65f57b
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/dsp/fir.py
+++ b/artiq/gateware/dsp/fir.py
@ -69,7 +69,7 @@ class ParallelFIR(Module):
        n = len(coefficients)
        # input and output: old to new, decreasing delay
        self.i = [Signal((width, True)) for i in range(p)]
-        self.o = [Signal((width, True)) for i in range(p)]
+        self.o = [Signal((width, True), reset_less=True) for i in range(p)]
        self.latency = (n + 1)//2//p + 2
        w = _widths[arch]