22 Commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	af0cd902d3	get frequency from RTIO, support fractional frequencies	2014-09-26 17:24:06 +08:00
Sebastien Bourdeauducq	538aaa4c14	rtio: fix o_error csr size	2014-09-25 12:54:26 +08:00
Sebastien Bourdeauducq	9b8a91e67e	rtio: increase FIFO sizes	2014-09-17 19:53:29 +08:00
Sebastien Bourdeauducq	d8b9543e1b	rtio: use FWFT FIFO with no buffering. This fixes replace operations.	2014-09-17 19:53:06 +08:00
Sebastien Bourdeauducq	b207a3cef5	rtio: remove ISE bug workaround	2014-09-12 16:15:32 +08:00
Sebastien Bourdeauducq	813bc90194	rtio: support readout of counter from software	2014-09-12 15:27:40 +08:00
Sebastien Bourdeauducq	7efc28ede1	soc/ad9858: do not drive FUD by default	2014-09-11 23:11:00 +08:00
Sebastien Bourdeauducq	1b58e1510d	soc/rtio: mini-channels	2014-09-11 23:09:43 +08:00
Sebastien Bourdeauducq	202284d44c	soc/rtio: software-controlled replace	2014-09-11 23:09:20 +08:00
Sebastien Bourdeauducq	a158b87d9f	rtio: collapse zero-length intervals	2014-09-10 21:21:02 +08:00
Sebastien Bourdeauducq	a580d44007	rtio: ignore series of writes with the same value and add pileup detection	2014-09-09 22:02:17 +08:00
Sebastien Bourdeauducq	8d7591dfcf	more PEP8	2014-09-05 17:06:41 +08:00
Sebastien Bourdeauducq	4915b4b5aa	PEP8	2014-09-05 12:03:22 +08:00
Sebastien Bourdeauducq	9e4bc35354	soc/rtio: input support	2014-07-25 16:23:35 -06:00
Sebastien Bourdeauducq	6b6b44b924	soc/rtio: mux OE	2014-07-25 11:09:26 -06:00
Sebastien Bourdeauducq	f03ae5e5b0	soc/rtio: separate PHY, add OE and fine timestamp in FIFO	2014-07-24 23:50:20 -06:00
Robert Jördens	005d66c7cd	soc/dds: fix timing	2014-07-22 17:44:41 -06:00
Sebastien Bourdeauducq	2358b218bf	soc: add DDS interface core	2014-07-22 11:37:53 -06:00
Sebastien Bourdeauducq	cdda1beea8	soc/rtio: refactor, share counter and underflow detector	2014-07-21 13:17:21 -06:00
Sebastien Bourdeauducq	5f58789592	rtio: fix FIFO WE	2014-07-20 18:22:53 -06:00
Sebastien Bourdeauducq	0cb18d58a8	rtio: add FIFO level CSR	2014-07-17 19:35:53 -06:00
Sebastien Bourdeauducq	3b4bb41a19	add basic output-only untested RTIO core	2014-07-16 19:13:11 -06:00