forked from M-Labs/artiq
soc/rtio: software-controlled replace
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800096f9a0
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202284d44c
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@ -13,6 +13,7 @@ class _RTIOBankO(Module):
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self.value = Signal(2)
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self.writable = Signal()
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self.we = Signal()
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self.replace = Signal()
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self.underflow = Signal()
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self.level = Signal(bits_for(fifo_depth))
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@ -22,23 +23,9 @@ class _RTIOBankO(Module):
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counter = Signal(counter_width, reset=counter_init)
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self.sync += counter.eq(counter + 1)
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# ignore series of writes with the same value
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we_filtered = Signal()
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prev_value = Signal(2)
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self.comb += we_filtered.eq(self.we & (self.value != prev_value))
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self.sync += If(self.we & self.writable, prev_value.eq(self.value))
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# collapse zero-length intervals
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replace = Signal()
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prev_ts_coarse = Signal(counter_width)
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self.sync += If(we_filtered & self.writable,
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prev_ts_coarse.eq(self.timestamp[fine_ts_width:]))
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self.comb += replace.eq(
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self.timestamp[fine_ts_width:] == prev_ts_coarse)
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# detect underflows
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self.sync += \
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If(we_filtered & self.writable,
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If((self.we & self.writable) | self.replace,
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If(self.timestamp[fine_ts_width:] < counter + 2,
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self.underflow.eq(1))
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)
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@ -51,12 +38,12 @@ class _RTIOBankO(Module):
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self.submodules += fifo
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fifos.append(fifo)
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# FIFO write
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# FIFO replace/write
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self.comb += [
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fifo.din.timestamp.eq(self.timestamp),
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fifo.din.value.eq(self.value),
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fifo.we.eq(we_filtered & (self.sel == n)),
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fifo.replace.eq(replace)
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fifo.we.eq((self.we | self.replace) & (self.sel == n)),
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fifo.replace.eq(self.replace)
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]
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# FIFO read
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@ -174,6 +161,7 @@ class RTIO(Module, AutoCSR):
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self._r_o_value = CSRStorage(2)
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self._r_o_writable = CSRStatus()
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self._r_o_we = CSR()
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self._r_o_replace = CSR()
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self._r_o_error = CSRStatus(2)
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self._r_o_level = CSRStatus(bits_for(ofifo_depth))
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@ -204,6 +192,7 @@ class RTIO(Module, AutoCSR):
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self.bank_o.value.eq(self._r_o_value.storage),
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self._r_o_writable.status.eq(self.bank_o.writable),
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self.bank_o.we.eq(self._r_o_we.re),
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self.bank_o.replace.eq(self._r_o_replace.re),
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self._r_o_error.status.eq(self.bank_o.underflow),
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self._r_o_level.status.eq(self.bank_o.level)
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]
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