forked from M-Labs/artiq
rtio: support readout of counter from software
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parent
10d796e026
commit
813bc90194
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@ -16,17 +16,16 @@ class _RTIOBankO(Module):
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self.replace = Signal()
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self.underflow = Signal()
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self.level = Signal(bits_for(fifo_depth))
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self.counter = Signal(counter_width, reset=counter_init)
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# # #
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# counter
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counter = Signal(counter_width, reset=counter_init)
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self.sync += counter.eq(counter + 1)
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self.sync += self.counter.eq(self.counter + 1)
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# detect underflows
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self.sync += \
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If((self.we & self.writable) | self.replace,
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If(self.timestamp[fine_ts_width:] < counter + 2,
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If(self.timestamp[fine_ts_width:] < self.counter + 2,
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self.underflow.eq(1))
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)
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@ -49,7 +48,7 @@ class _RTIOBankO(Module):
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# FIFO read
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self.comb += [
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chif.o_stb.eq(fifo.readable &
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(fifo.dout.timestamp[fine_ts_width:] == counter)),
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(fifo.dout.timestamp[fine_ts_width:] == self.counter)),
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chif.o_value.eq(fifo.dout.value),
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fifo.re.eq(chif.o_stb)
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]
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@ -171,6 +170,17 @@ class RTIO(Module, AutoCSR):
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self._r_i_re = CSR()
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self._r_i_error = CSRStatus(2)
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self._r_counter = CSRStatus(counter_width+fine_ts_width)
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self._r_counter_update = CSR()
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self._r_ise_workaround = CSRStatus(32) # FIXME: remove this
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# Counter
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self.sync += \
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If(self._r_counter_update.re,
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self._r_counter.status.eq(Cat(Replicate(0, fine_ts_width),
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self.bank_o.counter))
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)
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# OE
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oes = []
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for n, chif in enumerate(phy.rbus):
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