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rtio: support readout of counter from software

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This commit is contained in:
Sebastien Bourdeauducq 2014-09-12 15:27:40 +08:00
parent 10d796e026
commit 813bc90194
1 changed files with 15 additions and 5 deletions
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20
soc/artiqlib/rtio/core.py
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@ -16,17 +16,16 @@ class _RTIOBankO(Module):
self.replace = Signal()
self.underflow = Signal()
self.level = Signal(bits_for(fifo_depth))
self.counter = Signal(counter_width, reset=counter_init)
# # #
# counter
counter = Signal(counter_width, reset=counter_init)
self.sync += counter.eq(counter + 1)
self.sync += self.counter.eq(self.counter + 1)
# detect underflows
self.sync += \
If((self.we & self.writable) | self.replace,
If(self.timestamp[fine_ts_width:] < counter + 2,
If(self.timestamp[fine_ts_width:] < self.counter + 2,
self.underflow.eq(1))
)
@ -49,7 +48,7 @@ class _RTIOBankO(Module):
# FIFO read
self.comb += [
chif.o_stb.eq(fifo.readable &
(fifo.dout.timestamp[fine_ts_width:] == counter)),
(fifo.dout.timestamp[fine_ts_width:] == self.counter)),
chif.o_value.eq(fifo.dout.value),
fifo.re.eq(chif.o_stb)
]
@ -171,6 +170,17 @@ class RTIO(Module, AutoCSR):
self._r_i_re = CSR()
self._r_i_error = CSRStatus(2)
self._r_counter = CSRStatus(counter_width+fine_ts_width)
self._r_counter_update = CSR()
self._r_ise_workaround = CSRStatus(32) # FIXME: remove this
# Counter
self.sync += \
If(self._r_counter_update.re,
self._r_counter.status.eq(Cat(Replicate(0, fine_ts_width),
self.bank_o.counter))
)
# OE
oes = []
for n, chif in enumerate(phy.rbus):