forked from M-Labs/artiq
rtio: increase FIFO sizes
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@ -138,7 +138,7 @@ class _RTIOBankI(Module):
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class RTIO(Module, AutoCSR):
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def __init__(self, phy, counter_width=32, ofifo_depth=8, ififo_depth=8):
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def __init__(self, phy, counter_width=32, ofifo_depth=64, ififo_depth=64):
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fine_ts_width = get_fine_ts_width(phy.rbus)
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# Submodules
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