forked from M-Labs/artiq
rtio: remove ISE bug workaround
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@ -172,7 +172,6 @@ class RTIO(Module, AutoCSR):
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self._r_counter = CSRStatus(counter_width+fine_ts_width)
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self._r_counter_update = CSR()
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self._r_ise_workaround = CSRStatus(32) # FIXME: remove this
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# Counter
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self.sync += \
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