forked from M-Labs/artiq
soc/ad9858: do not drive FUD by default
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1b58e1510d
commit
7efc28ede1
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@ -33,7 +33,7 @@ class AD9858(Module):
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Round-trip addr A setup (> RX, RD, D to Z), RD prop, D valid (< D
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valid), D prop is ~15 + 10 + 20 + 10 = 55ns
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"""
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def __init__(self, pads, bus=None):
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def __init__(self, pads, drive_fud=False, bus=None):
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if bus is None:
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bus = wishbone.Interface()
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self.bus = bus
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@ -66,8 +66,9 @@ class AD9858(Module):
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bus.dat_r.eq(dr)
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)
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fud = Signal()
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self.sync += pads.fud_n.eq(~fud)
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if drive_fud:
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fud = Signal()
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self.sync += pads.fud_n.eq(~fud)
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pads.wr_n.reset = 1
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pads.rd_n.reset = 1
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@ -84,7 +85,7 @@ class AD9858(Module):
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If(bus.adr[0],
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NextState("GPIO")
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).Else(
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NextState("FUD")
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NextState("FUD") if drive_fud else None
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)
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).Else(
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If(bus.we,
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@ -144,19 +145,20 @@ class AD9858(Module):
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bus.ack.eq(1),
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NextState("IDLE")
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)
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if drive_fud:
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fsm.act("FUD",
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# 4ns FUD setup to SYNCLK
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# 0ns FUD hold to SYNCLK
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fud.eq(1),
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bus.ack.eq(1),
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NextState("IDLE")
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)
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fsm.act("GPIO",
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bus.ack.eq(1),
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bus_r_gpio.eq(1),
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If(bus.we, gpio_load.eq(1)),
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NextState("IDLE")
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)
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fsm.act("FUD",
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# 4ns FUD setup to SYNCLK
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# 0ns FUD hold to SYNCLK
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fud.eq(1),
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bus.ack.eq(1),
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NextState("IDLE")
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)
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def _test_gen():
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@ -191,7 +193,7 @@ class _TestPads:
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class _TB(Module):
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def __init__(self):
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pads = _TestPads()
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self.submodules.dut = AD9858(pads)
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self.submodules.dut = AD9858(pads, drive_fud=True)
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self.submodules.initiator = wishbone.Initiator(_test_gen())
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self.submodules.interconnect = wishbone.InterconnectPointToPoint(
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self.initiator.bus, self.dut.bus)
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