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3b4a40401a
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drtio: RTPacketMaster TX (WIP)
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2016-10-21 22:46:14 +08:00 |
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1e313afe64
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drtio: CrossDomainNotification
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2016-10-21 22:45:45 +08:00 |
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c71c4c89e0
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drtio: change data direction in _CrossDomainRequest
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2016-10-21 22:44:47 +08:00 |
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6a88229e6a
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drtio: CrossDomainRequest
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2016-10-20 23:37:59 +08:00 |
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9790c5d9ed
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drtio/iot: FIFO level
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2016-10-19 18:04:03 +08:00 |
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71480c4d15
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drtio: fix mmcm_mult
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2016-10-18 17:28:03 +08:00 |
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e7dbed3b02
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gateware: KC705 satellite target
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2016-10-17 19:23:45 +08:00 |
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9752ffe3d1
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drtio: various fixes
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2016-10-17 19:23:08 +08:00 |
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cce29e8b83
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gateware/spi: fix import
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2016-10-17 14:47:19 +08:00 |
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d3b274fc4d
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drtio: synchronizer MMCM
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2016-10-16 17:40:58 +08:00 |
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03d3a85e75
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drtio: RX clock alignment and ready
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2016-10-15 18:36:27 +08:00 |
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08e4aa3e3f
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drtio: GTX WIP
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2016-10-14 00:36:13 +08:00 |
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c548a65ec3
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drtio: clock domains
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2016-10-14 00:34:59 +08:00 |
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018f6d1b52
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drtio: implement basic IOT
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2016-10-11 17:59:22 +08:00 |
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a40b39e9a2
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drtio: structure
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2016-10-10 23:12:12 +08:00 |
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87ec333f55
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drtio: implement basic writes, errors, fifo levels on satellite
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2016-10-10 00:13:41 +08:00 |
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23b3302200
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drtio: implement TSC load in satellite
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2016-10-07 19:30:53 +08:00 |
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cb0d1549c6
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drtio: add rt_packets TX datapath, fixes
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2016-10-07 15:35:29 +08:00 |
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76bac21d14
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drtio: RT RX datapath, untested
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2016-10-06 18:51:20 +08:00 |
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1e0c6d6d5d
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drtio: monitor received link_init
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2016-09-30 11:25:06 +08:00 |
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cefb9e1405
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drtio: add full link layer
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2016-09-27 21:41:57 +08:00 |
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08772f7a71
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drtio: add RX ready signaling
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2016-09-27 19:02:54 +08:00 |
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95d7cba34a
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drtio: fixes, add aux packet test
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2016-09-27 12:46:01 +08:00 |
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e59142e344
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drtio: use additive scrambler reset by link init
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2016-09-27 11:38:05 +08:00 |
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8a92c2c7e5
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drtio: add RX link layer, fixes, simple loopback demo
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2016-09-27 11:23:29 +08:00 |
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4e47decdbc
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drtio: add scrambler/descrambler and test
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2016-09-26 14:14:14 +08:00 |
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fa83ad0d9c
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drtio: add TX link layer
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2016-09-26 12:53:10 +08:00 |
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8280e72e90
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gateware: use new misoc CSR mapping API
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2016-09-24 20:48:37 +08:00 |
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2bb90a4449
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pipistrello: shrink a few more fifos
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2016-09-21 02:29:05 +02:00 |
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a7dd356d30
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rtio/phy/ttl: support 'set sensitivity and sample' command (#218)
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2016-09-07 15:42:09 +08:00 |
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051e6e0447
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spi: use misoc SPIMachine, closes #314
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2016-08-26 14:08:12 +02:00 |
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92f3757c74
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spi: give wb-reads a register level
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2016-07-31 14:53:19 +02:00 |
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454b48df97
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pipistrello: shrink fifos a bit more to relax pnr
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2016-07-23 12:55:49 +02:00 |
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7a2405146a
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rtio: do not reset DDS and SPI PHYs on RTIO reset (#503)
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2016-07-09 10:07:19 +08:00 |
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8cb29fcb3b
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targets/kc705: redefine user SMAs as 3.3V IO. Closes #502
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2016-07-07 14:53:01 +08:00 |
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71921de5bd
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spi: do not shift when starting a xfer, closes #495
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2016-07-04 12:22:47 +02:00 |
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3bd190e624
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gateware/nist_clock: increase DDS bus drive strength. Closes #468
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2016-06-07 11:08:19 -04:00 |
|
dhslichter
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141edb521a
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qc2: swap SPI/TTL, all TTL lines are now In+Out compatible
|
2016-05-19 10:42:03 +08:00 |
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90e678a442
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gateware/nist_qc2: increase DDS bus drive strength. Closes #421
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2016-05-03 16:29:38 +08:00 |
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9707981c07
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targets/kc705: fix default -H option
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2016-04-30 00:30:24 +08:00 |
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212ee8ca35
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gateware/nist_qc2: substitute FMC
|
2016-04-14 01:02:34 +08:00 |
|
dhslichter
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f395a630e0
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Updated qc2 pinouts for SPI and 2x DDS bus, update docs
|
2016-04-13 18:38:34 +08:00 |
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ed1c368e73
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gateware: name targets consistently. Closes #290
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2016-04-05 16:07:29 +08:00 |
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8f54a1e619
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pipistrello: sys_clk 83 -> 75 MHz
This should close #341 once migen generates stable output.
|
2016-03-21 13:47:32 +01:00 |
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900b0cc629
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analyzer: make byte_count 64-bit
|
2016-03-19 19:40:23 +08:00 |
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0e1f75ec49
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targets/kc705/qc2: hook up HPC backplane
|
2016-03-16 16:19:56 +08:00 |
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1bbef94061
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analyzer: fix byte_count (again)
|
2016-03-15 20:49:07 +08:00 |
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85ea70a664
|
analyzer: fix byte_count
|
2016-03-15 20:33:08 +08:00 |
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62ac4e3c2e
|
analyzer: fix EOP generation
|
2016-03-15 20:25:02 +08:00 |
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b5ec979db3
|
analyzer: drive wishbone cyc signal
|
2016-03-15 19:46:12 +08:00 |
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