srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

analyzer: drive wishbone cyc signal

This commit is contained in:
Sebastien Bourdeauducq 2016-03-15 19:46:12 +08:00
parent a142d403ea
commit b5ec979db3
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
artiq/gateware/rtio/analyzer.py
View File

@ -175,6 +175,7 @@ class DMAWriter(Module, AutoCSR):
# # #
self.comb += [
membus.cyc.eq(self.sink.stb),
membus.stb.eq(self.sink.stb),
self.sink.ack.eq(membus.ack),
membus.we.eq(1),