forked from M-Labs/artiq
pipistrello: shrink a few more fifos
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9a24a81f14
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2bb90a4449
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@ -176,7 +176,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
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self.rtio_crg.rtiox4_stb)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=256,
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128,
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ofifo_depth=4))
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# the last TTL is used for ClockGen
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@ -223,7 +223,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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phy = dds.AD9858(dds_pins, 8)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=256,
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ofifo_depth=128,
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ififo_depth=4))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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