 Jack-Zheng
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22cd0f4c9d
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PCB: fix logo resolution issue, fix AG5300 module pin bug, update crystal package, add SMT positioning hole; FabricationOutput: add SMT position and BOM file
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2021-07-14 14:33:32 +08:00 |
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Jack-Zheng
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9aeb94f2c9
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PCB: add screw hole keep out
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2021-07-12 11:29:03 +08:00 |
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Jack-Zheng
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e0ef7d6e7f
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FPGA: fix IIC ESD protection bug
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2021-07-12 10:03:25 +08:00 |
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Jack-Zheng
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3a06817165
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CurrentSense: connect FAULT signal to MCU
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2021-07-09 16:07:40 +08:00 |
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Jack-Zheng
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3228e16c8f
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MCU, FPGA, Ethernet, PCB: fix decoupling capacitors
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2021-07-07 16:14:10 +08:00 |
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Jack-Zheng
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eceba52792
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PCB & FPGA & MCU: fix LVDS impedance issues
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2021-07-06 10:28:18 +08:00 |
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Jack-Zheng
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1b592eed37
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FPGA & MCU & PCB: add decoupling capactors
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2021-07-02 11:04:53 +08:00 |
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Jack-Zheng
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4853b02184
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PCB: replace 0201 resistors to 0402 as JLC cannot do SMT for 0201
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2021-06-30 14:59:13 +08:00 |
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Jack-Zheng
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26d727f8c5
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PCB: replace LVDS resistors with 0201 package, optimize LVDS pairs layout
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2021-06-29 16:49:26 +08:00 |
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Jack-Zheng
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4b15f466a0
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PCB: finish SWD, IIC
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2021-06-25 18:15:56 +08:00 |
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Jack-Zheng
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0e1120d266
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FPGA: modify pin connections for convenient layout routing; PCB: finish FPGA IO, FSMC, ADC BUS, Power routing
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2021-06-25 16:57:46 +08:00 |
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Jack-Zheng
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2a31c8b3f3
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PCB: finish LVDS routing
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2021-06-24 15:43:31 +08:00 |
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Jack-Zheng
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6535ff5423
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LVDS&IO: add fpga flash config; all: fix connection bugs; PCB: initialize component positions and layout
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2021-06-22 16:34:02 +08:00 |
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Jack-Zheng
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b740887ac2
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HighSpeedADC: fix chip rotation bug, remove SMA connector; all: fix BJT base resistors; Power: remove DC jack; LVDS&IO: replace IDC header with dupont
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2021-06-21 17:06:36 +08:00 |
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Jack-Zheng
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982fefd6b5
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all: update gitigore to fix symbol and footpin bugs; replace messy libs into one
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2021-06-21 16:05:17 +08:00 |
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Jack-Zheng
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9bcc9a229b
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TestAutomation: replace messy wires with bus
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2021-06-21 12:10:31 +08:00 |
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Jack-Zheng
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45940c1ac8
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all: finish routing
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2021-06-18 16:13:42 +08:00 |
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Jack-Zheng
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9c10edde19
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CurrentSensor: add mid point voltage reference; FPGA: fix pinout
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2021-06-18 14:24:15 +08:00 |
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Jack-Zheng
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0cebd6ed2b
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LVDS: add LVDS ports; all: add LEDs
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2021-06-18 11:30:16 +08:00 |
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Jack-Zheng
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74f4fc201a
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FPGA: add GPIO and ADC parallel port
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2021-06-18 10:27:05 +08:00 |
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Jack-Zheng
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9a62476f9e
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MCU: finish connectors
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2021-06-17 17:33:12 +08:00 |
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Jack-Zheng
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6cee2d0419
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Current_Senser: add current sampling; all: optimize +3.3VA
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2021-06-17 15:30:51 +08:00 |
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Jack-Zheng
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dfe4255a21
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MCU: finish FSMC, PWM
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2021-06-17 10:52:33 +08:00 |
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Jack-Zheng
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5b4801ff74
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FPGA: finish EEM, I2C, CFG, SPI FLASH
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2021-06-16 17:32:33 +08:00 |
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Jack-Zheng
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fc2cb47610
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all: map symbol and footpins
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2021-06-16 17:32:33 +08:00 |
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Jack-Zheng
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83bc618f77
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PowerSupply: finish PoE and 12V input schematic
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2021-06-16 17:32:32 +08:00 |
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Jack-Zheng
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232af06c28
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components confirmed; datasheet collected; framework finished
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2021-06-16 17:32:32 +08:00 |