Ryan Summers
|
4d0b1b5566
|
Reordering lib.rs
|
2021-01-20 13:44:53 +01:00 |
Ryan Summers
|
86355c9c5d
|
Removing main.rs
|
2021-01-20 13:44:16 +01:00 |
Ryan Summers
|
26677063ea
|
Adding support for multiple applications
|
2021-01-20 13:43:34 +01:00 |
Ryan Summers
|
058e474b78
|
Merge pull request #230 from vertigo-designs/feature/hardware-module
Refactoring to support multiple apps
|
2021-01-20 12:35:36 +01:00 |
Ryan Summers
|
573189bdd9
|
Fixing build
|
2021-01-18 17:23:21 +01:00 |
Ryan Summers
|
6618e921fe
|
Moving panic configuration
|
2021-01-18 16:55:56 +01:00 |
Ryan Summers
|
8dd72ae75e
|
Reordering
|
2021-01-18 16:52:09 +01:00 |
Ryan Summers
|
20535a721d
|
Refactoring to support multiple apps
|
2021-01-18 16:47:47 +01:00 |
Ryan Summers
|
d447501c47
|
Merge pull request #208 from vertigo-designs/feature/io-docs
Adding documentation, updating DAC output timing
|
2021-01-18 13:54:56 +01:00 |
Ryan Summers
|
7a2f950667
|
Updating timer compare offsets
|
2021-01-18 13:41:23 +01:00 |
Ryan Summers
|
598a48b178
|
Merge branch 'master' into feature/io-docs
|
2021-01-18 13:25:03 +01:00 |
Robert Jördens
|
1d0e1f9651
|
Merge pull request #222 from matthuszagh/lockin
Lockin
|
2021-01-13 18:47:37 +01:00 |
Matt Huszagh
|
9697560404
|
reciprocal_pll: remove unneeded type cast
|
2021-01-13 09:08:16 -08:00 |
Matt Huszagh
|
e599977983
|
revert changes in main.rs and server.rs
|
2021-01-13 08:59:27 -08:00 |
Matt Huszagh
|
76088efda5
|
dsp: add reciprocal_pll
|
2021-01-13 08:37:33 -08:00 |
Matt Huszagh
|
6aad92af43
|
fix bug in which real signal component is assigned twice
|
2021-01-12 18:36:18 -08:00 |
Matt Huszagh
|
07b7201b49
|
fix cargo fmt style
|
2021-01-12 17:26:42 -08:00 |
Matt Huszagh
|
a0d472b398
|
use only integer iir
|
2021-01-12 17:21:55 -08:00 |
Matt Huszagh
|
f974f4099c
|
remove TODO note relating ADC_BATCHES and calculate_timestamp_timer_period
Having both is not really redundant.
|
2021-01-12 16:17:58 -08:00 |
Matt Huszagh
|
80ed715f5a
|
shift sin/cos before demodulation product to avoid i64
|
2021-01-12 16:07:04 -08:00 |
Matt Huszagh
|
41ea2ebed4
|
use round up half integer rounding
|
2021-01-12 15:59:03 -08:00 |
Matt Huszagh
|
4c033c0f3e
|
move timestamp handling into new TimestampHandler struct
|
2021-01-12 13:06:49 -08:00 |
Matt Huszagh
|
e14aa8b613
|
move lock-in code to main.rs
|
2021-01-12 10:45:34 -08:00 |
Matt Huszagh
|
891aad3f17
|
remove debug_assert in divide_round
|
2021-01-12 07:43:28 -08:00 |
Matt Huszagh
|
31d23a3e0c
|
lock-in: use same method for batch_index branching in both instances
|
2021-01-12 07:36:56 -08:00 |
Matt Huszagh
|
bae295140d
|
update lock-in for integer math and PLL
|
2021-01-12 07:36:56 -08:00 |
Matt Huszagh
|
028f4a1bb2
|
fix small typos
|
2021-01-12 07:36:56 -08:00 |
Ryan Summers
|
ad3681f30b
|
Merge pull request #223 from quartiq/rs/issue-219/adc-setup
Conforming to external ADC conversion timing
|
2021-01-12 07:05:17 -08:00 |
Ryan Summers
|
db3a42a7b9
|
Update src/adc.rs
Co-authored-by: Robert Jördens <rj@quartiq.de>
|
2021-01-12 06:54:16 -08:00 |
Ryan Summers
|
bcf7a59993
|
Removing dac isr clear
|
2021-01-12 14:15:45 +01:00 |
Ryan Summers
|
09ecd3291a
|
Merge branch 'rs/issue-219/adc-setup' into feature/io-docs
|
2021-01-12 14:02:19 +01:00 |
Ryan Summers
|
6b170c25ed
|
Fixing timing synchronization
|
2021-01-12 13:29:15 +01:00 |
Ryan Summers
|
91975993cf
|
Fixing docs
|
2021-01-11 12:38:20 +01:00 |
Ryan Summers
|
d5c21efc9d
|
Adding extra DMA transfer to clear TXTF in ADC SPI transfers
|
2021-01-11 12:31:15 +01:00 |
Ryan Summers
|
1307ddb0ba
|
Merge pull request #196 from vertigo-designs/feature/pounder-timestamping
Feature/pounder timestamping
|
2021-01-11 01:50:09 -08:00 |
Robert Jördens
|
f785ec2f51
|
hitl: dispatch stabilizer event
|
2021-01-08 19:13:48 +01:00 |
Robert Jördens
|
09a7ab2773
|
ci: correctly use stable toolchain
|
2021-01-08 19:09:42 +01:00 |
Robert Jördens
|
96dc13da35
|
hitl: rename, add badge
|
2021-01-08 19:05:51 +01:00 |
Robert Jördens
|
5ecb28fb05
|
Merge pull request #220 from quartiq/jordens-hitl
hardware in the loop testing
|
2021-01-08 17:30:12 +01:00 |
Robert Jördens
|
72d69960ca
|
Create hitl.yml
|
2021-01-08 17:28:07 +01:00 |
Ryan Summers
|
5eab732d93
|
Adding information about DSP timing specifications
|
2021-01-06 15:38:04 +01:00 |
Ryan Summers
|
56366a013f
|
Specifying consequences of failing to meet timing
|
2021-01-06 15:34:12 +01:00 |
Ryan Summers
|
f6062c666e
|
Fixing pounder v1.1 build
|
2021-01-06 15:13:28 +01:00 |
Ryan Summers
|
4b3ceb0c0b
|
Merge branch 'feature/io-docs' of github.com:vertigo-designs/stabilizer into feature/io-docs
|
2021-01-06 15:12:25 +01:00 |
Ryan Summers
|
eefb2acfda
|
Updating dependencies
|
2021-01-06 15:12:03 +01:00 |
Ryan Summers
|
cd4721b506
|
Merge branch 'master' into feature/io-docs
|
2021-01-06 15:10:30 +01:00 |
Ryan Summers
|
f825f52785
|
Apply suggestions from code review
Co-authored-by: Robert Jördens <rj@quartiq.de>
|
2021-01-06 06:08:07 -08:00 |
Ryan Summers
|
18068082ac
|
Fixing CI
|
2021-01-06 15:04:06 +01:00 |
Ryan Summers
|
e9cef7bbac
|
Fixing after review
|
2021-01-06 14:59:01 +01:00 |
Ryan Summers
|
29a89637f8
|
Merge branch 'master' into feature/pounder-timestamping
|
2021-01-06 14:45:56 +01:00 |