fsagbuya
/
zynq-rs
forked from M-Labs/zynq-rs
1
0
Fork 0
Code Pull Requests Activity
616 Commits 3 Branches 0 Tags 1.4 MiB
Commit Graph

616 Commits

Author SHA1 Message Date
Astro ce74fe7299 eth: prepare tx 2019-06-22 01:39:44 +02:00
Astro ec5dda4d0a eth: add const MTU 2019-06-22 01:34:17 +02:00
Astro 6757ceb76c eth rx: error handling 2019-06-22 01:20:18 +02:00
Astro 98947961c6 linker script: bump stack size to 64k 
for all the network buffers
 2019-06-22 00:48:54 +02:00
Astro a4be03bee9 rx: PktRef 2019-06-21 01:19:04 +02:00
Astro 80f003b2c6 stdio: add print 2019-06-21 01:18:24 +02:00
Astro e5881a14ad eth rx: descriptors/buffers as refs 
avoid moving these after their addresses have been written to the qbar
 2019-06-21 00:58:18 +02:00
Astro d65398205f add a println! for convenience 2019-06-20 00:30:18 +02:00
Astro b3b65f9b74 eth: find Phy 2019-06-19 00:21:17 +02:00
Astro 54d0f3583d eth: fix io configuration 
phy detection now works
 2019-06-18 23:10:35 +02:00
Astro 1634513bc7 mmu: align l1_table 2019-06-18 19:18:47 +02:00
Astro 9bebfb49bc begin MMU implementation 2019-06-17 03:32:10 +02:00
Astro 69b65b5f72 cortex_a9 regs: allow defining bit fields 2019-06-17 01:36:11 +02:00
Astro 1e16beb707 cortex_a9::regs: use crate::regs interface 2019-06-12 00:20:23 +02:00
Astro 81a892b618 eth: recv_next() 2019-06-10 02:44:29 +02:00
Astro f92ea3b99d eth: start_tx 2019-06-09 20:28:33 +02:00
Astro f07a541c99 eth: model rx/tx state with type parameters 2019-06-09 20:10:41 +02:00
Astro 74bd81f87f eth: add safety asserts 2019-06-09 02:23:37 +02:00
Astro 824e91e6cb eth: rx/tx desc list, start_rx 2019-06-09 01:02:10 +02:00
Astro 2d7fed6c59 link again compiler_builtins 
required for memset etc
 2019-06-09 01:00:58 +02:00
Astro d447f1cc45 main: probe for PHYs 2019-06-04 23:50:11 +02:00
Astro b9ca9324f0 eth: fix initialization 2019-06-04 23:48:33 +02:00
Astro 6d15b82a3e cortex_a9::regs: init U bit for unaligned access 2019-06-04 23:47:23 +02:00
Astro acf995d7da soft_reset: rm unreachable! 2019-05-31 00:19:20 +02:00
Astro bf4f5108f4 main: add UART_RATE 2019-05-31 00:19:01 +02:00
Astro 2f27ff574f improve linker script 2019-05-31 00:17:53 +02:00
Astro 2df74cc055 add static exception handling 2019-05-30 20:30:19 +02:00
Astro b13bf72c17 eth: begin phy communication 2019-05-30 02:42:42 +02:00
Astro 5b15bb5c0a main: make boot_core0() naked 2019-05-30 02:41:44 +02:00
Astro c0610ad66a slcr: init gem* rclk/clk 2019-05-30 02:26:19 +02:00
Astro ee7ae7f7cc slcr: add soft_rst() 2019-05-30 00:24:51 +02:00
Astro b961526b97 uart: remove type conversion from baud_rate_gen 2019-05-30 00:22:45 +02:00
Astro a645d13f4b add uart panic handler 2019-05-28 00:28:35 +02:00
Astro 75bb755327 extend linker script 2019-05-27 22:38:10 +02:00
Astro d10ffe9eb9 eth: setup mio_pins, configure net_cfg 2019-05-25 03:06:39 +02:00
Astro 51c39f032e run with the cora z7-10 2019-05-25 02:38:48 +02:00
Astro b3da0e4c93 slcr: define all mio_pin regs, typed io_type 2019-05-25 02:34:58 +02:00
Astro 6bf210366a regs: properly emit doc_comments 2019-05-24 23:49:49 +02:00
Astro 56c2f1d833 eth: add net_status, phy_maint registers 2019-05-24 00:20:59 +02:00
Astro ad77e3dc04 eth: add net_cfg register 2019-05-24 00:06:29 +02:00
Astro 402b8c9ab1 eth: no unsafe, note, add qbar register fields 2019-05-23 23:18:36 +02:00
Astro 1033648c3e add l1_cache_init() 2019-05-23 19:05:06 +02:00
Astro 179c617904 add register_bits_typed! macro 2019-05-23 18:29:05 +02:00
Astro 785e726661 RegisterW/RegisterRW: required &mut self for safety 2019-05-23 18:01:18 +02:00
Astro 62ca26fa71 slcr: abstract with RegisterBlock 2019-05-23 17:52:06 +02:00
Astro fd7fd0db14 main: rm unused feature #![feature(global_asm)] 2019-05-23 16:06:41 +02:00
Astro 99371375fd Cargo.toml: don't disable lto for profile.release 2019-05-23 16:06:17 +02:00
Astro ea62d4fdec uart: make baudrate configurable, run at 115,200 baud 2019-05-23 15:50:53 +02:00
Astro 15883293ac uart: use div_round_closest in baud_rate_gen 2019-05-23 15:37:07 +02:00
Astro 7428fec200 uart: add more channel_sts flags, wait for tx_fifo_empty() before sending 2019-05-23 15:36:34 +02:00