fsagbuya/zynq-rs
1
0
Fork 0
forked from M-Labs/zynq-rs
Code Pull Requests Activity

main: probe for PHYs

Browse Source
This commit is contained in:
Astro 2019-06-04 23:49:06 +02:00
parent b9ca9324f0
commit d447f1cc45
1 changed files with 13 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
src/main.rs
View File

@ -77,15 +77,21 @@ const UART_RATE: u32 = 115_200;
fn main() {
let mut uart = Uart::serial(UART_RATE);
loop {
for i in 0.. {
writeln!(uart, "i={}\r", i);
}
}
writeln!(uart, "\r\nHello World!\r");
let eth = eth::Eth::default();
loop {
let mut eth = eth::Eth::default();
writeln!(uart, "Eth on\r");
use eth::phy::PhyAccess;
for addr in 1..=31 {
let detect = eth.read_phy(addr, 1);
let id1 = eth.read_phy(addr, 2);
let id2 = eth.read_phy(addr, 3);
writeln!(uart, "phy {}: {:04X} {:04X} {:04X}\r", addr, detect, id1, id2);
}
while !uart.tx_fifo_empty() {}
loop {}
panic!("End");
}
#[panic_handler]