fsagbuya/zynq-rs
1
0
Fork 0
forked from M-Labs/zynq-rs
Code Pull Requests Activity

slcr: add soft_rst()

Browse Source
This commit is contained in:
Astro 2019-05-30 00:23:31 +02:00
parent b961526b97
commit ee7ae7f7cc
1 changed files with 14 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
src/slcr.rs
View File

@ -66,7 +66,7 @@ pub struct RegisterBlock {
reserved2: [u32; 5],
pub clk_621_true: RW<u32>,
reserved3: [u32; 14],
pub pss_rst_ctrl: RW<u32>,
pub pss_rst_ctrl: PssRstCtrl,
pub ddr_rst_ctrl: RW<u32>,
pub topsw_rst_ctrl: RW<u32>,
pub dmac_rst_ctrl: RW<u32>,
@ -207,6 +207,16 @@ impl RegisterBlock {
self_.slcr_lock.lock();
r
}
/// Perform a soft reset
pub fn soft_reset(&mut self) -> ! {
self.pss_rst_ctrl.write(
PssRstCtrl::zeroed()
.soft_rst(true)
);
unreachable!()
}
}
register!(slcr_lock, SlcrLock, WO, u32);
@ -305,6 +315,9 @@ impl UartRstCtrl {
}
}
register!(pss_rst_ctrl, PssRstCtrl, RW, u32);
register_bit!(pss_rst_ctrl, soft_rst, 1);
/// Used for MioPin*.io_type
#[repr(u8)]
pub enum IoBufferType {