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d8c40ce382
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Add failing trace and trace analysis
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2020-10-20 13:05:38 +08:00 |
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b9481cecf5
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Reduce lane count to 4 for easier debugging
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2020-10-20 11:40:19 +08:00 |
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8fe67cf6f4
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Skip assertions for configurable no. of clock cycles
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2020-10-19 12:39:32 +08:00 |
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5011245007
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Increase BMC depth for sorting network assertions
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2020-10-16 13:41:38 +08:00 |
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036c91539b
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Start preparing assertions for sorting network
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2020-10-16 12:18:09 +08:00 |
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ec957ad411
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Fix keyword argument issue for read_port in rtio.cri
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2020-10-15 13:11:06 +08:00 |
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b4ec588630
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Fix keyword argument issue in rtio.cri
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2020-10-14 17:26:38 +08:00 |
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6746052a60
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Add rtio.sed.output_driver
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2020-10-09 11:16:01 +08:00 |
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1d5945f7fa
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Add rtio.sed.output_network
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2020-10-08 17:05:04 +08:00 |
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c2ee2fbdef
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Add rtio.sed.layouts
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2020-10-08 11:06:35 +08:00 |
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fd1b469322
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Remove redundant (object) in rtio.rtlink
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2020-10-08 09:34:29 +08:00 |
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1f838186e8
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Add rtio.rtlink
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2020-10-07 16:32:20 +08:00 |
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85d1523b52
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Add rtio.cri
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2020-10-07 12:01:37 +08:00 |
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8d3c69ea08
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Remove redundant files
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2020-09-30 12:33:50 +08:00 |
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c9857bb831
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Reset translation progress
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2020-09-30 10:55:08 +08:00 |
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a3cdb44572
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Add WIP implementation of rtio.sed.output_driver
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2020-09-29 17:27:43 +08:00 |
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36fb6306b0
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Add rtio.sed.output_network
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2020-09-29 16:35:59 +08:00 |
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7c742dc2d1
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Add rtio.sed.lane_distributor
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2020-09-28 16:01:43 +08:00 |
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bf08fe1d50
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Add partial implementation of lane distributor
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2020-09-28 11:36:26 +08:00 |
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49684c1990
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Add partial implementation of CRI interface
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2020-09-25 16:27:56 +08:00 |
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1a83778590
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Remove redundant 'artiq.gateware' from module names
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2020-09-25 15:10:07 +08:00 |
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