Reduce lane count to 4 for easier debugging
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@ -11,7 +11,7 @@ class OutputNetworkTestCase(FHDLTestCase):
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def verify(self):
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# Bounded model check
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self.assertFormal(
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OutputNetwork(16, 2, [("data", 32), ("channel", 3)], fv_mode=True),
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OutputNetwork(4, 2, [("data", 32), ("channel", 3)], fv_mode=True),
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mode="bmc", depth=40)
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# TODO: unbounded proof
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